You are given a T flip-flop module with the following declaration:
module tff ( input clk, input reset, // active-high synchronous reset input t, // toggle output q );
Write a testbench that instantiates one tff and will reset the T flip-flop then toggle it to the "1" state.
编写一个测试台,实例化一个tff,重置T触发器,然后将其切换到“1”状态。
这里随便写就行,有一个reset的重置,有t的赋值变化
module top_module ();
reg clk;
reg reset;
reg t;
wire q;
tff u_tff(clk,reset,t ,q) ;
initial begin
clk=1'b0;
forever
#10
clk=~clk;
end
initial begin
reset = 1'b0;t=0;
#10;
reset = 1'b1;
#10;
reset = 1'b0; t=1;
end
endmodule