数字电路设计之自动综合出single port ram

module ram_infer (q, a, d, we, clk);
output reg [7:0] q;
input [7:0] d;
input [6:0] a;
input we, clk;
reg [7:0] mem [127:0];
always @ (posedge clk) begin
if (we)
mem[a] <= d;
q <= mem[a]; // Non-blocking write assignment means
                        // q doesn't get d in this clock cycle
end
endmodule

参考资料：http://bbs.eetop.cn/thread-401306-1-1.html

                    http://xilinx.eetop.cn/viewthread-102928

                    还可以参考我之前写的一篇博客