LTspice仿真mos上升延时和下降延时

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文件 SPICE_param_0.35um.txt

-问题1
•按照以下步骤评估上升和下降延迟时间。
1.通过SPICE DC（.DC）分析获得pMOS和nMOS的I-V曲线，其中|Vgs|=Vdd，并计算逆变器的等效电阻。（注意）等效电阻有许多可能的定义，然后解释您的定义。
2.假设漏极和体之间的电压为0，计算栅极电容和漏极扩散电容。假设SiO2的相对介电常数为3.8。（注）该电压假设旨在估计电压相关扩散电容的最大电容值，而体通常连接到源极。
3.使用（1）和（2）的结果，计算相关逆变器驱动四个相同逆变器时的逆变器延迟时间。假设一个阶跃输入。
4.通过SPICE瞬态（。输入转换时间设置为0.02 ns。（添加可选）讨论（3）和（4）之间不匹配的原因。
问题2
•绘制一张图表，包括通过SPICE模拟评估的上升和下降延迟时间。X轴是从0pF到0.5pF的负载电容。Y轴是延迟时间。
问题3
•现在，该逆变器需要驱动4pF的大负载，这对于给定逆变器来说太大了。然后，我们将多个逆变器并联并减小等效电阻。此外，我们还改变了逆变器级的数量。通过优化每级的级数和并联逆变器的数量，最小化延迟（此处定义为上升和下降延迟时间的平均值）。请注意，图中包括第一个逆变器的级数必须为偶数。解释您的设计策略和设计结果，并显示SPICE获得的延迟时间。

- Problem 1

• Evaluate rise and fall delay times following the steps below.

1. Obtain I-V curves of pMOS and nMOS by SPICE DC (.dc) analysis, where |Vgs|=Vdd, and calculate the equivalent resistance of the inverter. (Note) There are many possible definitions of equivalent resistance, and then explain your definition.

2.Calculate gate capacitance and drain diffusion capacitance assuming the voltage between drain and body is 0. Suppose relative permittivity of SiO2 is 3.8. (Note) This voltage assumption aims to estimate the maximum capacitance value of the voltage- dependent diffusion capacitance, while body is usually connected to source.

3.Using the results of (1) and (2), calculate the inverter delay times in case that the inverter of interest drive four identical inverters. Assume a step input.

4.Compute the delay times of (3) by SPICE transient (.tran) simulation numerically. The input transition time is set to 0.02 ns. (Optional for score addition) Discuss the reason for the mismatch between (3) and (4).

Problem 2

• Draw a graph that includes rise and fall delay times evaluated by SPICE simulation. X-axis is the load capacitance ranging from 0pF to 0.5pF. Y-axis is the delay time.

Problem 3

• Now, this inverter needs to drive a large load of 4pF, which is too large for the given inverter. Then, we connect multiple inverters in parallel and reduce the equivalent resistance. Also, we change the number of inverter stages. Minimize the delay, which is defined as the average of rise and fall delay times here, by optimizing the number of stages and the number of inverters in parallel for each stage. Note that the number of stages, which includes the first inverter in the figure, must be an even number. Explain your design strategy and your design result and show the delay time obtained by SPICE.