verilog基础篇--常用的信号生成模块

背景

有时候被叫写一些简单的测试信号，翻来覆去的写。这里我留个底，下次直接复制这些模块。

常用信号

1、//模块功能:产生脉宽可调的周期脉冲信号

//模块功能:产生脉宽可调的周期脉冲信号
`timescale 1ns / 1ns

module pulse_gen_module # (
    parameter PULSE_WIDTH_W = 16
    )(
    input                     rst,
    input                     clk,
    input  [PULSE_WIDTH_W-1:0] width,  // pulse width  这里参数要减去1
    input  [PULSE_WIDTH_W-1:0] period, // pulse period   这里参数要减去1
    															//最终功能仿真无误

    output                    pulse
    );
    
    reg [PULSE_WIDTH_W-1:0] period_cnt =  'b0;
    always @ (posedge clk) begin//: pulse_cnt_proc
        if (rst)
            period_cnt <=  'b0;
        else
            period_cnt <= (period_cnt < period) ? (period_cnt + 1'b1) : 'b0;
    end
    
    reg pulse_r = 1'b0;
    always @ (posedge clk) begin//: pulse_gen_proc
        if (rst)
            pulse_r <= 1'b0;
        else
            pulse_r <= (period_cnt <= width) ? 1'b1 : 1'b0;
    end
    
    assign pulse = pulse_r;

    
endmodule

2、产生周期可调的方波信号

always @ (posedge sysclk or negedge rst)
	begin
		if(!rst)
		time_cnt<=0;
		else if (time_cnt=='d50_000_0)
		time_cnt<=0;
		else
		time_cnt<=time_cnt+1'b1;
	end

always @ (posedge sysclk or negedge rst)
	begin
		if(!rst)
		led_reg<=0;
		else if(time_cnt=='d50_000_0)
		led_reg<=~led_reg;
		else
		led_reg<=led_reg;
	end
assign led=led_reg;
endmodule