Intel FPGA I/O input delay 和output delay约束的例子

例子来自《Quartus Prime TimeQuest Timing Analyzer Cookbook》

讲了关于如何约束I/O管脚delay的问题。大致思路是，约束实际的时钟和生成虚拟的时钟，设置硬件delay参数，根据input delay 和output delay的计算公式进行约束。以下为原文。

Input and Output Delays with Virtual Clocks

All input and output delays should reference a virtual clock. With that virtual clock, the TimeQuest
analyzer can derive and apply the correct clock uncertainty values when you use the derive_clock_uncertainty command. If the input and output delays reference base clocks or PLL
clocks rather than virtual clocks, the intra- and inter-clock transfer clock uncertainties, determined by derive_clock_uncertainty , are incorrectly applied to the I/O ports. Also, with virtual clocks, additional external clock uncertainties can be applied independent of the clock uncertainties determined by derive_clock_uncertainty.

The properties of the virtual clock should be identical to the original clock used to clock either the input (input delay) or output (output delay) ports.

Example 12: Input and Output Delays Referencing a Virtual Clock

#create the input clock
create_clock -name clkA -period 10 [get_ports clkA]
#create the associated virtual input clock
create_clock -name clkA_virt -period 10
#create the output clock
create_clock -name clkB -period 5 [get_ports clkB]
#create the associated virtual input clock
create_clock -name clkB_virt -period 5
#determine internal clock uncertainties
derive_clock_uncertainty
#create the input delay referencing the virtual clock
#specify the maximum external clock delay from the external
#device
set CLKAs_max 0.200
#specify the minimum external clock delay from the external
#device
set CLKAs_min 0.100
#specify the maximum external clock delay to the FPGA
set CLKAd_max 0.200
#specify the minimum external clock delay to the FPGA
set CLKAd_min 0.100
#specify the maximum clock-to-out of the external device
set tCOa_max 0.525
#specify the minimum clock-to-out of the external device
set tCOa_min 0.415

#specify the maximum board delay
set BDa_max 0.180
#specify the minimum board delay
set BDa_min 0.120
#create the input maximum delay for the data input to the
#FPGA that accounts for all delays specified
set_input_delay -clock clkA_virt \
-max [expr $CLKAs_max + $tCOa_max + $BDa_max - $CLKAd_min] \
[get_ports {data_in[*]}]
#create the input minimum delay for the data input to the
#FPGA that accounts for all delays specified
set_input_delay -clock clkA_virt \
-min [expr $CLKAs_min + $tCOa_min + $BDa_min - $CLKAd_max] \
[get_ports {data_in[*]}]
#creating the output delay referencing the virtual clock
#specify the maximum external clock delay to the FPGA
set CLKBs_max 0.100
#specify the minimum external clock delay to the FPGA
set CLKBs_min 0.050
#specify the maximum external clock delay to the external device
set CLKBd_max 0.100
#specify the minimum external clock delay to the external device
set CLKBd_min 0.050
#specify the maximum setup time of the external device
set tSUb 0.500
#specify the hold time of the external device
set tHb 0.400
#specify the maximum board delay
set BDb_max 0.100
#specify the minimum board delay
set BDb_min 0.080
#create the output maximum delay for the data output from the
#FPGA that accounts for all delays specified
set_output_delay -clock clkB_virt \
-max [expr $CLKBs_max + $tSUb + $BDb_max - $CLKBd_min] \
[get_ports {data_out}]
#create the output minimum delay for the data output from the
#FPGA that accounts for all delays specified
set_output_delay -clock clkB_virt \
-min [expr $CLKBs_min - $tHb + $BDb_min - $CLKBd_max] \
[get_ports {data_out}]