Verilog语言实现可重叠序列检测器（10010）（Mealy型和Moore型）

1.Mealy型

输出不仅与当前状态有关，还和输入有关

1.1 代码(三段式)

module check_10010( clk, rst_n, din, dout

    );//Mealy
    input clk, rst_n, din;
    output reg dout;
    reg [2:0] current_state, next_state;
    parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b011, S3 = 3'b010, S4 = 3'b110;
    
    always@(posedge clk or negedge rst_n)
        begin
        if(!rst_n)
            current_state <= S0;
        else
            current_state <= next_state;
        end
        
    always@(current_state or din)
        begin
            case(current_state)
            S0:begin if (din == 1) next_state = S1;
                else next_state = S0;end
            S1:begin if (din == 1) next_state = S1;
                else next_state = S2;end
            S2:begin if (din == 1) next_state = S1;
                else