PC通过USB读写FPGA

	`timescale 1ns / 1ps
	//-------------------------------------------------------
	// Create Date:    08:57:17 04/22/2012 
	// Design Name: 
	// Module Name:    USB_FPGA 
	//-------------------------------------------------------
	//pc read 512bytes from card
	//pc write >=64bytes to card
	module USB_FPGA(
	input  clk,
	inout [15:0] fdata,
	output reg [1:0] faddr,
	output reg slrd ,
	output reg slwr,
	input flagd,
	input flaga,
	output reg sloe,
	//
	output reg				wrreq,
	output reg [15:0] 	data,
	//
	output reg		fifo_out_rdreq,
	input [15:0] 	fifo_out_q,
	input 			fifo_out_rdfull,
	input [8:0] 	fifo_out_rdusedw
	);	 
	//
	reg [8:0] pc_wr_cnt;
	reg [8:0] wr_cnt;
	reg    	 wr_valid;
	reg [1:0] state=0;
	parameter READ1=0;
	parameter READ2=1;
	parameter WRITE1=2;
	parameter WRITE2=3; 
	assign fdata= ((state==WRITE2)||(state==READ1)) ? fifo_out_q : 16'hzzzz;

	//-------------------------------------------------------
	always @(posedge clk)
	begin
	case(state)
	READ1: 
		begin
		faddr<=2'b00;
		slrd<=1;
		sloe<=0;
		state<=READ2;
		wrreq <= 0;
		fifo_out_rdreq <= 1'b0;
		end
	READ2:
		begin
		state <= WRITE1;
		if(flaga)//not empty,read one byte,then turn to WRITE
			begin
			slrd  <= 0;
			data  <= fdata;
			if(pc_wr_cnt < 9'd64) begin wrreq <= 1; end
			end
		else
			begin 
			slrd  <= 1;
			wrreq <= 0;
			end
		end
	WRITE1:
		begin
		wrreq <= 0;
		slrd  <= 1;
		sloe  <= 1;
		faddr <= 2'b10;
		state<=WRITE2;
		if(wr_valid) 
			begin
			fifo_out_rdreq <= 1'b1;
			end
		end
	WRITE2:
		begin
		fifo_out_rdreq <= 1'b0;
		state<=READ1;
		end
	default:
		begin
		faddr<=2'b00;
		sloe<=1;
		slrd<=1;
		fifo_out_rdreq <= 1'b0;
		state<=READ1;
		end
	endcase 
	end	
	//-------------------------------------------------------
	
	
	//-------------------------------------------------------
	always @(posedge clk)
	begin
		if(flaga)
			begin
			if(wrreq) pc_wr_cnt <= pc_wr_cnt + 1;
			end
		else pc_wr_cnt <= 9'd0;
	end
	//-------------------------------------------------------
  
	
	//-------------------------------------------------------
	always @(posedge clk)
	begin slwr <= ~fifo_out_rdreq; end
	//-------------------------------------------------------

	
	//-------------------------------------------------------
	always @(posedge clk)
	begin
	if(wr_valid)
		begin if(~slwr) wr_cnt <= wr_cnt + 1; end
	else wr_cnt <= 9'd0;
	end
	//-------------------------------------------------------
	
	
	always @(posedge clk)
	begin
	if(wr_cnt == 9'd256) wr_valid <= 1'b0;
	else if(fifo_out_rdusedw == 9'd256) wr_valid <= 1'b1;
	end
	
	
	endmodule