“The APU uses an external GICv2 controller as a central resource to support and manage interrupts. There are peripheral interrupts, software generated interrupts, and virtual interrupts.”即包含三类中断:PI SGI VI
"Peripheral interrupts are asserted by a signal to the GIC. The GIC architecture defines the following types of peripheral interrupts. • Private peripheral interrupt (PPI) is a peripheral interrupt that is specific to a single processor. • Shared peripheral interrupt (SPI) is a peripheral interrupt that the distributor can route to any of a specified combination of processors. These are wired interrupts coming from various sources to the GIC. Each peripheral interrupt is either edge-triggered or level-sensitive."即PI由GIC来掌控,包含PPI SPI
“The APU uses an external GICv2 controller as a central resource to support and manageinterrupts. There are peripheral interrupts, software generated interrupts, and virtualinterrupts.”即包含三类中断:PI SGI VI"Peripheral interrupts are asserted by a signal to