HDLBits学习笔记（二）

Dff（D触发器）

A D flip-flop is a circuit that stores a bit and is updated periodically, at the (usually) positive edge of a clock signal.

D触发器存储1bit数据一般是上边缘触发

 

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//
    always @(posedge clk) begin
        q <= d;//时序逻辑电路通常使用非阻塞赋值
    end
    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments

endmodule

Edgedetect

For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and pedge[1] are shown separately.

检测输入位数的变化，检测上升沿

module top_module(
	input clk,
	input [7:0] in,
	output reg [7:0] pedge);
	
	reg [7:0] d_last;	
			
	always @(posedge clk) begin
		d_last <= in;			//记住前一个循环的状态
		pedge <= in & ~d_last;	//如果输入为0则出现上升沿，此时刻为1
	end
	
endmodule

Edgedetect2

For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.

检测输入位数的变化，检测双边沿

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0] s_lst;
    always @(posedge clk) begin
        s_lst <= in;
        anyedge <= in^s_lst;
    end
endmodule

Edgecapture

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the 'reset' event occurs one cycle earlier than the 'set' event, so there is no conflict here.

功能：检测下降沿变化后置输出为1，一直保持直到复位为高

与上升沿检测类似：out= 上一时刻输入 & 此时输入（取反），因为要保持为1，此时再与输出或运算即可

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] s_lst;
    always @(posedge clk) begin
        s_lst<=in;
        if(reset)
            out<=32'b0;
        else
        	out<=~in&s_lst|out;
    end
endmodule

刚开始将s_lst<=in写到了else内，时序图出错，原因：HDLBits-Edgecapture_hdlbits edgecapture_葱白有滋味的博客-CSDN博客

Dualedge

You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.

fpga不支持双边沿触发器即always @(posedge clk or negedge clk)，但是用门电路即可搭建起双边沿触发器

module top_module(
    input clk,
    input d,
    output q);
    
    reg p, n;
    
    // A positive-edge triggered flip-flop
    always @(posedge clk)
        p <= d ^ n;
        
    // A negative-edge triggered flip-flop
    always @(negedge clk)
        n <= d ^ p;
    
    // At each (positive or negative) clock edge, p and n FFs alternately
    // load a value that will cancel out the other and cause the new value of d to remain.
    assign q = p ^ n;
    
endmodule

实现方法：

// Why does this work? 
// After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
// After negedge clk, n changes to p^n. Thus q = (p^n) = (p^d^p) = d.
//即满足了双边沿下q<=d的实现