SystemVerilog中`define传参
---带参数的Macro Function
一、用Macro定義簡單的function,使代碼變得簡潔明了
module top ;
`define A_SRAM_RW(dst_cc_num,src_cc_num)\
if(strm_sel[``dst_cc_num``] == 1'b1)begin\
force top.my_dut.strm_in``dst_cc_num``_en = top.my_dut.strm_in``src_cc_num``_en;\
end
initial begin
`A_SRAM_RW(1,0)
`A_SRAM_RW(2,0)
end
endmodule
-
對上面的代碼進行仿真
module top;
initial begin
if(strm_sel[1] == 1'b1)begin
force top.my_dut.strm_in1_en = top.my_dut.strm_in0_en;
end
if(strm_sel[2] == 1'b1)begin
force top.my_dut.strm_in2_en = top.my_dut.strm_in0_en;
end
end
endmodule
- 上面的例子中,dst_cc_num和src_cc_num是要传进来的参数
- 引用传进来的参数时要在参数前和后加``,不接收传进来的变量
- 比如
generate
for(genvar jj=1;jj<`CC_NUM;jj++)begin
`A_SRAM_RW(jj,0)
end
endgenerate
- 上面这种写法是不行的,相当于只是把jj传进了define中,并不会把jj所代表的值传进去。
//From reading these it might be apparent that define macro can be used for adding a postfix to the variable,
//but not prefix. I was thinking the same after reading the description (they don't have a single example of
//adding prefix to the variable via `define. Confused ?? Let me explain by giving a concrete example
view sourceprint?
// Example macro for a coverage class
// Aim : want to get ABC_cp : coverpoint ABC {bins b = {1}; }
// by calling `COV(ABC)
`define COV(__name) __name``_cp : coverpoint __name {bins b = {1}; }
// Next
// What to do if I want cp_ABC in place of ABC_cp as for the above example
// NOTE : I can't use cp_``__name as cp_ is not an input to the macro
// Solution
// Use nested macros
`define PREFIX(__prefix, __name) __prefix``__name
`define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }
二、把macro当做字符串
`define MEM_PATH htl_top.xxx_top.xxxx.RAM_Row_0_Col_0.uut
function mem_backdoor_api(string hdl_path, int index, mem_array[2048]);
endfunction : mem_backdoor_api
mem_backdoor_api(`"`MEM_PATH`", i, mem_array[i]);