HDLBits练习Count clock

最新推荐文章于 2024-09-10 08:04:30 发布

han_shazi

最新推荐文章于 2024-09-10 08:04:30 发布

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文章标签： Verilog 计数器时钟同步电路数字逻辑

本文链接：https://blog.csdn.net/han_shazi/article/details/126806141

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module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
//second counter
always@(posedge clk)begin
if (reset)
ss[3:0]<=4'h0;
else if(ss[3:0]==4'd9&&ena)
ss[3:0]<=4'd0;
else if(ena)
ss[3:0]<=ss[3:0]+4'd1;
end
always@(posedge clk)begin
if (reset)
ss[7:4]<=4'h0;
else if(ss==8'h59&&ena)
ss[7:4]<=4'd0;
else if(ss[3:0]==4'd9&&ena)
ss[7:4]<=ss[7:4]+4'd1;
end
//minute counter
always@(posedge clk)begin
if (reset)
mm[3:0]<=4'h0;
else if(mm[3:0]==4'd9&&ss==8'h59&&ena)
mm[3:0]<=4'd0;
else if(ss==8'h59&&ena)
mm[3:0]<=mm[3:0]+4'd1;
end
always@(posedge clk)begin
if (reset)
mm[7:4]<=4'h0;
else if(mm==8'h59&&ss==8'h59&&ena)
mm[7:4]<=4'd0;
else if(mm[3:0]==4'd9&&ss==8'h59&&ena)
mm[7:4]<=mm[7:4]+4'd1;
end
//hour counter
always@(posedge clk)begin
if (reset)
hh[3:0]<=4'h2;
else if(hh[3:0]==4'd9&&mm==8'h59&&ss==8'h59&&ena)
hh[3:0]<=4'd0;
else if(hh!=8'h12&&mm==8'h59&&ss==8'h59&&ena)
hh[3:0]<=hh[3:0]+4'd1;
else if(hh==8'h12&&mm==8'h59&&ss==8'h59&&ena)
hh[3:0]<=4'h1;
end
always@(posedge clk)begin
if (reset)
hh[7:4]<=4'h1;
else if(hh==8'h12&&mm==8'h59&&ss==8'h59&&ena)
hh[7:4]<=4'h0;
else if(hh[3:0]==4'd9&&mm==8'h59&&ss==8'h59&&ena)
hh[7:4]<=hh[7:4]+4'd1;
end
always@(posedge clk)begin
if(reset)
pm<=1'b0;
else if(hh==8'h11&&mm==8'h59&&ss==8'h59&&ena)
pm=~pm;
end
endmodule