trailing edge:clock的第二个沿
leading edge:clock的第一个沿
^:如果在输入pin上,指该pin的输入edge为上升沿;如果在输出pin上,指该pin的输出edge为上升沿;
v:如果在输入pin上,指该pin的输入edge为下降沿;如果在输出pin上,指该pin的输出edge为下降沿;
create_clock -name ck1 -period 4 -waveform {0 2}
create_clock -name ck2 -period 4 -waveform {2 4}
report_clocks clk_name:ck1和ck2得到的结果完全相同。(report_clock是根据leading edge和trailing edge进行report)
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Clock Name Source View Period Lead Trail Generated Propagated
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ck1 - NA 4.000 0.000 2.000 n n
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get_property [get_clocks ck1] period
4.000
get_property [get_clocks ck2] period
4.000
get_property [get_clocks ck1] waveform
{0.000000 2.000000}
get_property [get_clocks ck2] waveform
{2.000000 4.000000}