做后端时,经常听到setup timing检查下一沿,hold timing检查同沿。这句话究竟对不对?它的本质逻辑又在哪里呢?今天来剖析一下:
从定义上讲setup time和hold time。
setup time:
the setup timing check ensures that the data is available at the input of the flipflop before it is clocked in the flipflop. The data should be stable for a certain amount of time, this time is called setup time.
所以从定义上来理解,即为FF2的setup time检查的是从FF1来的信号传输至FF2时是否有足够的setup time,使FF2的clk信号到来时,读取的信号是正确的。check timing中检查的主体为-to reg(即为FF2),而在信号传输过程中,FF1的信号要早于FF2的信号一个周期。所以对于FF2而言,它的setup timing check其实是check上一个沿 FF1触发后传输来的信号到达FF2的Dpin时是否满足setup time。
所以从FF1的信号传输至FF2的信号所需要的时间为Tlaunch+Tdata(即arrival time)。而FF2抓取到FF1输出信号的时间为Tcapture+T。
考虑cell需要的setup time,design的uncertainty,为使信号稳定,FF1传输来的信号所需要的最小时间为:Tcapture+T-Tsetup-Tunc(即required time)
所以slack time = required time - arrival time = Tcapture+T-Tsetup-Tunc - (Tlaunch+Tdata)
hold time:
hold time: the hold timing check ensures that a flipflop output value that is changing dose not pass through to a capture flipflop and overwrite its output before the flipflop has had a chance to capture its original value. The hold specification of a flipflop requires that the data being latched should be held stable for a specified amount of time after the active edge of the clock.
hold time check的主体依然是-to reg(即为FF2)。与setup需要抓住上一级输出信号所以本级要顺延一个周期的理解逻辑不同。hold没有引入前后级概念,只是抓到信号后需要保持的时间。
本级信号的传输时间为Tlaunch+Tdata(arrival time),本级信号的时间为Tcapture
考虑hold time,uncertainty,信号最小需要保持的时间:Tcapture+Thold+Tunc(required time)
所以slack time = arrival time - required time = Tlaunch+Tdata - (Tcapture+Thold+Tunc)
至于为什么cell需要setup time和hold time,可以参考这个链接:
其实不管是setup还是hold check,关键问题在于找到endpoint的capture edge。hold check是用capture edge去check同一级launch edge,setup check用capture edge去check前一级的laucnch edge。以低电平latch为例:
当setup和hold同时有问题时,如何fix?
https://zhuanlan.zhihu.com/p/91111805?utm_source=wechat_session
latch应用总结: