一篇关于setup time和hold time的问答

Q：
Can any body tell me
1) What causes HOLD VIOLATIONS in DESIGN.
2) How it effects DESIGN.
3) What changes need to be done to make DESIGN work.



A1：A synchronous design uses FF devices. A FF device needs its data to be valid
before and after rising clock edge. The time before edge is called setup time
and the one after edge is called hold time. While the former may be overcome
by having a faster device, temperature or power supply restrictions the latter can not.
In FPGA devices always use dedicated clock pins. Some FPGA devices allow the
insertion of delay at an input pad to eliminate hold time requirement.
Note that FPGA vendors usually do not specify minimum clock to output
delay of an outgoing FF device. So if your design is driven by an FPGA
and you need positive (> 0) hold time you might face a problem.

More info, VHDL and VERILOG code as well as simulation utilities can  be found at
http://bknpk.no-ip.biz/






A2：1) What causes HOLD VIOLATIONS in DESIGN.
Simply, data should be hold for some time (hold time) after the edge of the clock. So, if the data changes with the hold time might cause violation. In general, hold time will be fixed during backend work (during PNR) while buildingclock tree. If u r a frontend designer, concentrate on fixing setup time violations rather than hold violations .

2) How it effects DESIGN.
If a chip is done with some setup violations it can work by reducing the frequency.
If achip is done with hold violations , JUST DUMP the chip. This is how it effects at the end of the day. Hold vilations needs to be fixed.

3) What changes need to be done to make DESIGN work.
PNR tools will route and place the cells in such a way that no timing violations will occur. If  still u face hold violations , u can manully work on it to fix. Manually place the cells to avoid hold violations , or in the worst case, u can keep some buffers in the datapath to avoid hold violations (but be sure setup timing is not effected.)




>you said "If a chip is done with hold violations, JUST DUMP the chip. "
>why can't reducing the frequency to settle the hold violation as setup violation ?
>could you explain it clearer ?

Equation for Setup Time
Tclk > Tclktoq + Tlogic + Tsetup + Tskew + Tjitter
Equation for Hold Time
Tclktoq + Tlogic - Tskew > Thold

Note that Hold Time equation is independent of clk frequency(i.e Time period Tclk)
key things to note from above equations
a) once the silicon comes back , if u have setup time problem , u can
increase the clock period (Tclk) to fix it , whereas if u have hold
time problem , its a more serious problem and u will need a new
metal fix tapeout . ( But u can still test the current chip using Low supply voltage,
or High temperature or SS corner part that decrease hold time violation)> Hi koggestone,
> It is nice information. Could you please give us more information on
> " u will need a new metal fix tapeout . ( But u can still test the current chip using
> Low supply voltage, or High temperature or SS corner part that decrease hold time >violation)"

what i meant was , when u have hold time violation , u dont need to throw away chip and wait for 3 months for fixed chip to come back. in the meanwhile , by playing with voltage and temperature , u can do other functional tests on the chip . since normally hold time simulation are done at " FF corner , high voltage, low temperature " which is the pessimistic case for hold time , by decreasing voltage , using high temperature, and a SS corner chip , we may be lucky enough to find a part that works , to do other functional tests to catch any other bugs before next tapeout.