Depletion and enhancement modes
In field-effect transistors (FETs), depletion mode and enhancement mode are two major transistor types, corresponding to whether the transistor is in an on state or an off state at zero gate–source voltage.
Enhancement-mode MOSFETs (metal–oxide–semiconductor FETs) are the common switching elements in most integrated circuits. These devices are off at zero gate–source voltage. NMOS can be turned on by pulling the gate voltage higher than the source voltage, PMOS can be turned on by pulling the gate voltage lower than the source voltage. In most circuits, this means pulling an enhancement-mode MOSFET’s gate voltage towards its drain voltage turns it on.
In a depletion-mode MOSFET, the device is normally on at zero gate–source voltage. Such devices are used as load “resistors” in logic circuits (in depletion-load NMOS logic, for example). For N-type depletion-load devices, the threshold voltage might be about −3 V, so it could be turned off by pulling the gate 3 V negative (the drain, by comparison, is more positive than the source in NMOS). In PMOS, the polarities are reversed.
The mode can be determined by the sign of the threshold voltage (gate voltage relative to source voltage at the point where an inversion layer just forms in the channel): for an N-type FET, enhancement-mode devices have positive thresholds, and depletion-mode devices have negative thresholds; for a P-type FET, enhancement-mode have negative, and depletion-mode have positive.
Naming Rules
To help you remember which one is which, the reason they’re named this way is that if you put a gate voltage on an enhancement mode MOSFET, you are enhancing the number of free carriers, making it so it can conduct. Whereas if you put an opposite gate voltage on a depletion mode MOSFET, you are depleting the number of free carriers, stopping its ability to conduct.
1万+
被折叠的 条评论
为什么被折叠?
到【灌水乐园】发言
