参数化的interface array的例化及虚接口传递

在验证环境中，某个UVC常常需要多次例化，对应的interface也要多次例化。那么如何定义一个interface的数组以及接口配置呢？可以参考如下示例：

parameter logic[7:0] data_width[`NUM_OF_IF] = {16,32,16,8,16};               // inst. an array of data_width per each interfaces. Max value can be 255 (8 bits).
 
generate
     for(genvar i=0; i<`NUM_OF_IF; i++) begin
         vpsc_internal_if  #(.DW(data_width[i])) vpsc_inst (.clk(clk), .reset_n(rst_n));    
 
         initial begin 
             uvm_config_db #(virtual vpsc_internal_if  #(.DW(data_width[i])) )::set(null, "uvm_test_top.env", $sformatf("vpsc_internal_vif_%0d", i), vpsc_inst);
             // set each interface to its fit virtual interface with config_db
         end //initial
     end //for
endgenerate

我们对以上代码做点改动，在for循环中增加虚接口定义和赋值，如下：

parameter logic[7:0] data_width[`NUM_OF_IF] = {16,32,16,8,16};               // inst. an array of data_width per each interfaces. Max value can be 255 (8 bits).
 
generate
     for(genvar i=0; i<`NUM_OF_IF; i++) begin
         vpsc_internal_if  #(.DW(data_width[i])) vpsc_inst (.clk(clk), .reset_n(rst_n));    
 		 virtual psc_internal_if  #(.DW(data_width[i])) vpsc_internal_vif ;
 		 vpsc_internal_vif = vpsc_inst ;
 		 
         initial begin 
             uvm_config_db #(virtual vpsc_internal_if  #(.DW(data_width[i])) )::set(null, "uvm_test_top.env", $sformatf("vpsc_internal_vif_%0d", i), vpsc_inst);
             // set each interface to its fit virtual interface with config_db
         end //initial
     end //for
endgenerate

编译时会报错：vpsc_internal_vif = vpsc_inst ;

修改后编译通过：

parameter logic[7:0] data_width[`NUM_OF_IF] = {16,32,16,8,16};               // inst. an array of data_width per each interfaces. Max value can be 255 (8 bits).
 
generate
     for(genvar i=0; i<`NUM_OF_IF; i++) begin
         vpsc_internal_if  #(.DW(data_width[i])) vpsc_inst (.clk(clk), .reset_n(rst_n));    
 		 virtual psc_internal_if  #(.DW(data_width[i])) vpsc_internal_vif = vpsc_inst ;
 		 
         initial begin 
             uvm_config_db #(virtual vpsc_internal_if  #(.DW(data_width[i])) )::set(null, "uvm_test_top.env", $sformatf("vpsc_internal_vif_%0d", i), vpsc_inst);
             // set each interface to its fit virtual interface with config_db
         end //initial
     end //for
endgenerate

注意：

1. parameter的赋值只能来自其他的parameter
2. 虚接口的参数配置需要和真实接口的参数配置一致
3. 模块或接口实例的数组不能被视为常规数组(regular arrays)，因为参数化、生成块和defparam语句(parameterization, generate blocks, and defparam statements )会使数组实例的元素不唯一。对于arrays of variables/wires，这是不可能发生的。

参考资料：

1. https://verificationacademy.com/forums/uvm/array-interfaces-systemverilog-parameters-how-create-array-and-set-it-configdb-virtual-interaces-array
2. https://forums.accellera.org/topic/6841-array-of-systemverilog-interface/