FPGA学习日记（19）--IP核

 

module pll
(   
    input     wire   sys_clk     ,
    output    wire   clk_mul_2   ,
    output    wire   clk_div     ,
    output    wire   clk_pha_90  ,
    output    wire   clk_duc_20  ,
    output    wire   locked     
);                    
pll_ip	pll_ip_inst
(
	.inclk0 ( sys_clk    ),
	.c0     ( clk_mul_2  ),
	.c1     ( clk_div    ),
	.c2     ( clk_pha_90 ),
	.c3     ( clk_duc_20 ),
	.locked ( locked     )
);
endmodule

`timescale 1ns/1ns
module tb_pll();

reg sys_clk ;


 wire   clk_mul_2   ;
 wire   clk_div     ;
 wire   clk_pha_90  ;
 wire   clk_duc_20  ;
 wire   locked      ;

initial 
    begin 
        sys_clk =1'b1;

    end
 
always #10 sys_clk = ~sys_clk;

pll pll_inst
(   
   .sys_clk    (sys_clk   ) ,
   .clk_mul_2  (clk_mul_2 ) ,
   .clk_div    (clk_div   ) ,
   .clk_pha_90 (clk_pha_90) ,
   .clk_duc_20 (clk_duc_20) ,
   .locked     (locked    )
);  
endmodule

时钟信号50Mhz

c0 二倍频 100Mhz

 

c1 二分频 25Mhz 

 5ns=0.25时钟周期 偏移90度 延迟5ns等于偏移90度

 c3 50MHz  20ns

 高电平保持时间4ns  占空比20%