补发 FPGA学习日记（4）半加器

finiteyhy

已于 2022-07-27 15:59:36 修改

阅读量118

点赞数

分类专栏： FPGA

于 2022-07-27 12:35:26 首次发布

本文链接：https://blog.csdn.net/jsomin/article/details/126002823

版权

Verilog 数字逻辑模块设计异或运算测试bench

关键词由CSDN通过智能技术生成

FPGA 专栏收录该内容

21 篇文章 2 订阅

订阅专栏

module half_addr

module half_addr
(
    input  wire in1,
    input  wire in2,
    output reg sum,
    output reg count
);

always@(*)
    case({in1,in2})
        2'b00:begin sum <=0;count<=0;   end
        2'b01:begin sum <=1;count<=0;   end
        2'b10:begin sum <=1; count<=0;  end
        2'b11:begin sum <=0; count<=1;  end
        default:begin sum <=0;count<=0; end
    endcase

//assign{count,sum} = in1 + in2;

endmodule

tb_module

`timescale 1ns/1ns
module tb_half_addr

reg in1;
reg in2;
wire sum;
wire count;

initial
    begin
        in1 <= 1'b0;
        in2 <= 1'b0;
    end

always #10 in1 <={$random}%2;
always #10 in2 <={$random}%2;


initial
    begin
        $timeformat(-9,0,"ns");
        $monitor("@time %t:in1= %b,in2 = %b,sum=%b,count=%b",$time,in1,in2,sum,count);
    end

half_addr half_addr_inst
(
    .in1(in1),
    .in2(in2),
    .sum(sum),
    .count(count)
);
endmodule