夏宇闻复习笔记第12章：同步状态机设计

12.1 moore机&mealy机

mealy机
输出信号=G(当前状态，输入信号)

moore机
输出信号=G(当前状态)

p168 12.1 三段式状态机实例

/******************************p168 12.1 三段式状态机实例********************************/
module  StateMachine0(rst_n,clk,A,k);
input               rst_n,clk;
input               A;
reg         [3:0]   Now_State;
output  reg [3:0]   Next_State；
output      [1:0]   k;

//独热码
parameter   IDLE    =   4'b0001;
            START   =   4'b0010;
            STOP    =   4'b0100;
            CLEAR   =   4'b1000;

//状态转换为时序逻辑       
always@(posedge clk or negedge rst_n)   begin
    if(!rst_n)  State   <=  IDLE;
    else        State   <=  Next_State;
end

//next状态的case设置为组合逻辑
always@(state or A)   begin
    case(state) 
        IDLE:       if(A)   Next_state  =   START;
                    else    Next_State  =   IDLE;
        START:      if(!A)  Next_State  =   STOP;
                    else    Next_State  =   START;
        STOP:       if(A)   Next_State  =   CLEAR;
                    else    Next_State  =   STOP;
        CLEAR:      if(!A)  Next_State  =   IDLE;
                    else    Next_State  =   CLEAR;
        default:            Next_State  =   IDLE;
end

//输出为组合逻辑
always@(state or rst_n or A)   begin
    if(!rst_n)                  k   =   2'b00;
    else if(state==STOP && A)   k   =   2'b10;
    else if(state==CLEAR && !A) k   =   2'b01;
    else                        k   =   2'b00;
end

endmodule

测试模块

/******************************p174 12.2 状态机测试模块********************************/
`timescale  1ns/1ns
module  test;
reg             A,clk,rst_n;
wire    [1:0]   k;

initial begin
    A=0;
    rst_n=1;
    #10;
    rst_n=0;
    #10;
    repeat(10)  begin
        #50 A={$random} %2;
    end
    rst_n=1;
    #10;
    $finish;
end

always  #10 clk=~clk;

StateMachine0   fsm0(.clk(clk),.rst_n(rst_n),.A(A),.k(k));

endmodule