HDLBits刷题记录 Circuits—Sequential Logic—Shift Registers

· 32-bit LFSR 

 思路：向量分割

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 
    always @(posedge clk) begin
        if (reset)	q <= 32'h1;
        else begin
            q[31] <= q[0] ^ 0;
            q[30:22] <= q[31:23];
            q[21] <= q[22] ^ q[0];
            q[20:2] <= q[21:3];
            q[1] <= q[2] ^ q[0];
            q[0] <= q[1] ^ q[0];
        end
    end
            
            

endmodule

· Shift register (Muxdff)

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //
    wire w2, w1, w0;
    MUXDFF u3 (SW[3], KEY, LEDR[3]);
    MUXDFF u2 (SW[2], {w2, KEY[2:0]}, LEDR[2]);
    MUXDFF u1 (SW[1], {w1, KEY[2:0]}, LEDR[1]);
    MUXDFF u0 (SW[0], {w0, KEY[2:0]}, LEDR[0]);
    
    assign w2 = LEDR[3];
    assign w1 = LEDR[2];
    assign w0 = LEDR[1];

endmodule

module MUXDFF (
	input SW,
    input [3:0] KEY,
	output LEDR);
    
    always @(posedge KEY[0]) begin
        LEDR <= KEY[2] ? SW : (KEY[1] ? KEY[3] : LEDR);
    end

endmodule

· 3-input LUT (简单内存及查找表)

注意：查找表可将索引作变量用 即q[{input1,input2,...}]  (0001对应q[1])

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    
    reg [7:0] q;
    always @(posedge clk) begin
        if (enable)	 q <= {q[6:0], S};
        else	q <= q;
    end
    
    assign Z = q[{A,B,C}];


endmodule