门控时钟检查

A clock gating check occurs when a gating signal can control the path of a clock signal at a logic cell. An example is shown in Figure 10-10. The pin of the logic cell connected to the clock is called theclock pin and the pin where the gating signal is connected to is the gating pin. The logic cell where the clock gating occurs is also referred to as thegating cell.

One condition for a clock gating check is that the clock that goes through the cell must be used as a clock downstream. The downstream clock usage can be either as a flip-flop clock or it can fanout to an output port or as a generated clock that refers to the output of the gating cell as its master. If the clock is not used as a clock after the gating cell, then no clock gating check is inferred.

Another condition for the clock gating check applies to the gating signal. The signal at the gating pin of the