Simple FSM

1.  Simple FSM1 asy reset

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        case(state)
            A:
                begin
                    if(in==1'b1) next_state=A;
                    if(in==1'b0) next_state=B;
                end
            B:
                begin
                    if(in==1'b1) next_state=B;
                    if(in==1'b0) next_state=A;
                end
        endcase
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset)
            state<=B;
        else
            state<=next_state;
    end

    assign out=state;

endmodule

2. Simple FSM1 sy reset

module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    parameter A=0;
    parameter B=1;

    reg present_state, next_state;

    always@(*)
        begin
           case (present_state)
                A:
                    begin
                        if(in==1'b1) next_state=A;
                        if(in==1'b0) next_state=B;
                    end
                B:
                    begin
                        if(in==1'b1) next_state=B;
                        if(in==1'b0) next_state=A;
                    end
            endcase 
        end
    
    always @(posedge clk) begin
        if (reset) begin  
            present_state=B;
        end else begin
            // State flip-flops
            present_state = next_state;             
        end
    end
    
    assign out=present_state;

endmodule

3.simple FSM2 asy

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  
 
    parameter OFF=0, ON=1; 
    reg state, next_state;
 
    always @(*) begin
        case(state)
            OFF:
                begin
                    if(j==0) next_state = OFF;
                    else next_state = ON;
                end
            ON:
                begin
                    if(k==0) next_state =  ON;
                    else next_state = OFF;
                end
        endcase
    end
 
    always @(posedge clk, posedge areset) begin
        if(areset)
            state <= OFF;
        else state <= next_state;
    end
 
    
    assign out = (state == ON);
 
endmodule

4.simple FSM2 sy

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  
 
    parameter OFF=0, ON=1; 
    reg state, next_state;
 
    always @(*) begin
        case(state)
            OFF:
                begin
                    if(j==0) next_state = OFF;
                    else next_state = ON;
                end
            ON:
                begin
                    if(k==0) next_state = ON;
                    else next_state = OFF;
                end
        endcase
    end
 
    always @(posedge clk) begin
        if(reset)
            state <= OFF;
        else
            begin
               state <= next_state; 
            end
    end
 
    
    assign out = (state == ON);
 
endmodule

5.simple state transitions 3

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //
 
    parameter A=0, B=1, C=2, D=3;
 
    // State transition logic: next_state = f(state, in)
    always@(*)
        begin
            case(state)
               A:
                   begin
                       if(in==0) next_state = A;
                       else next_state = B;
                   end
                B:
                   begin
                       if(in==0) next_state = C;
                       else next_state = B;
                   end
                C:
                   begin
                       if(in==0) next_state = A;
                       else next_state = D;
                   end
                D:
                   begin
                       if(in==0) next_state = C;
                       else next_state = B;
                   end
           endcase
        end
 
    // Output logic:  out = f(state) for a Moore state machine
    assign out = (state == D);
 
endmodule

6. simple one-hot state transitions 3

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //
 
    parameter A=0, B=1, C=2, D=3;
 
    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = (state[A]&~in)|(state[C]&~in);
    assign next_state[B] = (state[A]&in)|(state[B]&in)|(state[D]&in);
    assign next_state[C] = (state[B]&~in)|(state[D]&~in);
    assign next_state[D] = (state[C]&in);
 
    // Output logic: 
    assign out = state[D];
 
endmodule

7.Simple  FSM3 asy

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
 
    parameter A=2'd0;
    parameter B=2'd1;
    parameter C=2'd2;
    parameter D=2'd3;
    
    reg[1:0] state;
    reg[1:0] next_state;
    
    // State transition logic
    always@(*)
        begin
            case(state)
                A:
                    begin
                        if(in==0) next_state = A;
                        else next_state = B;
                    end
                B:
                    begin
                        if(in==0) next_state = C;
                        else next_state = B;
                    end
                C:
                    begin
                        if(in==0) next_state = A;
                        else next_state = D;
                    end
                D:
                    begin
                        if(in==0) next_state = C;
                        else next_state = B;
                    end
            endcase
        end
 
    // State flip-flops with asynchronous reset
    always@(posedge clk or posedge areset)
        begin
            if(areset)
                state = A;
            else
                state = next_state;
        end
 
    // Output logic
    assign out = (state == D);
 
endmodule

8.Simple FSM3 sy

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
 
    parameter A=2'd0;
    parameter B=2'd1;
    parameter C=2'd2;
    parameter D=2'd3;
    
    reg[1:0] state;
    reg[1:0] next_state;
    
    // State transition logic
    always@(*)
        begin
            case(state)
                A:
                    begin
                        if(in==0) next_state = A;
                        else next_state = B;
                    end
                B:
                    begin
                        if(in==0) next_state = C;
                        else next_state = B;
                    end
                C:
                    begin
                        if(in==0) next_state = A;
                        else next_state = D;
                    end
                D:
                    begin
                        if(in==0) next_state = C;
                        else next_state = B;
                    end
            endcase
        end
 
    // State flip-flops with asynchronous reset
    always@(posedge clk )
        begin
            if(reset)
                state = A;
            else
                state = next_state;
        end
 
    // Output logic
    assign out = (state == D);
 
endmodule

 

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