module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter A2=3'd0;
parameter B1=3'd1;
parameter B2=3'd2;
parameter C1=3'd3;
parameter C2=3'd4;
parameter D1=3'd5;
reg[2:0] state;
reg[2:0] next_state;
always @(*)begin
case(state)
A2:next_state = s[1]?B1:A2;
B1:next_state = s[2]?C1:(s[1]?B1:A2);
B2:next_state = s[2]?C1:(s[1]?B2:A2);
C1:next_state = s[3]?D1:(s[2]?C1:B2);
C2:next_state = s[3]?D1:(s[2]?C2:B2);
D1:next_state = s[3]?D1:C2;
default:next_state = 'x;
endcase
end
always @(posedge clk)begin
if(reset)begin
state <= A2;
end
else begin
state <= next_state;
end
end
always @(*)begin
case(state)
A2:{fr3,fr2,fr1,dfr} = 4'b1111;
B1:{fr3,fr2,fr1,dfr} = 4'b0110;
B2:{fr3,fr2,fr1,dfr} = 4'b0111;
C1:{fr3,fr2,fr1,dfr} = 4'b0010;
C2:{fr3,fr2,fr1,dfr} = 4'b0011;
D1:{fr3,fr2,fr1,dfr} = 4'b0000;
default:{fr3,fr2,fr1,dfr} = 'x;
endcase
end
endmodule
Design a moore FSM
最新推荐文章于 2024-08-16 19:56:55 发布