进入Non_project模式:
vivado -mode tcl
source top.tcl
top.tcl的内容为:
set _part “型号”
file mkdir project
read_verilog [glob *.v]
read_ip ip.xci //IP ooc
set_property file_type {Verilog Header} [get_files include.v] //beforce this step ,ensure that include.v has already read in
read_xdc xxx.xdc
synth_design -top "top module" -part "型号"
write_checkpoint -force "综合后dcp文件名"
#******************ILA***********************************#
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_prop