模块M0
`timescale 1ns/100ps
`define clk_cyc 50
module sigdata(rst,data,sclk,ack);
input ack;
output rst;
output [3:0] data;
output sclk;
reg rst;
reg sclk;
reg [3:0] data;
initial
begin
rst <= 1;
#10rst=0;
#(`clk_cyc*2+3)rst=1;
end
initial
begin
sclk = 0;
data = 0;
#(`clk_cyc * 1000) $stop;
end
always #(`clk_cyc) sclk = ~sclk;
always @(posedge ack)
begin
#(`clk_cyc/2+3) data = data+1;
end
endmodule
模块M1
module ptosda(rst,sclk,data,ack,scl,sda);
input rst,sclk;
input [3:0] data; //并行口数据输入
output ack; //请求新的转换数据
output scl;
output sda; //定义SDA为单向的串行输出
reg ack;
reg scl;
reg link_sda;
reg sdabuf;
reg [3:0] databuf;
reg [7:0] state;
assign sda = link_sda?sdabuf:1'b0; //link_sda控制sdabuf输出到串行总线上
parameter ready = 8'b0000_0000,
start = 8'b0000_0001,
bit3 = 8'b0000_0010,
bit2 = 8'b0000_0100,
bit1 = 8'b0000_1000,
bit0 = 8'b0001_0000,
prestop = 8'b0010_0000,
stop = 8'b0100_0000,
idle = 8'b1000_0000;
always@(posedge sclk or negedge rst