CMOS PROCESS FLOW 简化版总结 CMOS制造工艺流程 IC后端版图【VLSI】

Fabrication Facility 前言

Fabrication Facility：主要包括这些工序：Fabrication silicon wafer，也就是从砂中提纯单晶硅造wafer，现在主流wafer大小是200mm和300mm。Wafer processing，就是在wafer上制作芯片。建议可以先看这个视频了解一些形象化的概念：How are microchips made?

Fabrication of CMOS transistors as IC’s can be done in three different methods

• The N-well / P-well technology, where n-type diffusion is done over a p-type substrate or p-type diffusion is done over n-type substrate respectively.CMOS can be obtained by integrating both NMOS and PMOS transistors over the same silicon wafer.

• The Twin well technology, where NMOS and PMOS transistor are developed over the wafer by simultaneous diffusion over an epitaxial growth base, rather than a substrate.

• The silicon On Insulator process, where rather than using silicon as the substrate an insulator material is used to improve speed and latch-up susceptibility.

本文简单扼要地叙述了基于N阱技术的CMOS制造工艺流程（CMOS PROCESS FLOW Through the N-well / P-well technology），并制作为表格的形式，方便对照记忆和理解CMOS工艺。

CMOS PROCESS FLOW （CMOS制造工艺流程【全】）

The CMOS fabrication process flow is conducted using twenty basic fabrication steps while manufactured using N- well/P-well technology.

step	manufacturing processes	picture	Describes in detail
1	Choose a Substrate as a base		Choose a Substrate as a base for fabrication For N-well, a P-type silicon substrate is selectedFor P-well, a N-type silicon substrate is selected
2	Oxidation		Thermal silicon dioxide is the primary insulating film material employed in semiconductor device manufacture, can be formed by direct oxidation of the substrate, to form a “pad” thermal silicon dioxide layer on the wafer surface, which protects portions the substrate(base) of the wafer against contamination
3	Growing of Photoresist		Aim: Thermal silicon dioxide is the primary insulating film material employed in semiconductor device manufacture, can be formed by direct oxidation of the substrate, to form a “pad” thermal silicon dioxide layer on the wafer surface, which protects portions the substrate(base) of the wafer against contamination . Way: Dry oxidations grow SiO2 on top of Si wafer at 900 – 1200 C with H2O or O2in oxidation furnace, are normally used only when silicon dioxide film thicknesses of less than 100 nm are needed. In some cases, it can also use Thermal Oxidation. Si + O 2 → SiO 2 ps: The next step is the deposition of a layer of silicon nitride over the pad oxide. This layer acts as a stop for the chemical mechanical polishing (CMP) step later in the process. Silicon nitride thin films can be deposited by Low Pressure Chemical Vapor Deposition (LPCVD) using the chemical reaction: 3SiH 2 Cl 2 + 10NH 3 → Si 3 N 4 + 6NH 4 Cl + 6H 2
4	Masking		To “selectively” expose areas of the wafer to any given processing step (oxidation, deposition, implantation, etching, …) , the wafer is coated with a uniform film of a photosensitive emulsion.It is formed a Photoresist layer, which is a light-sensitive polymer that softens whenever exposed to light. way: A photoresist layer is deposited on the silicon nitride using a method known as spin coating. Centrifugal force drives the photoresist solution to the edges of the substrate and a layer of photoresist with a very uniform thickness across the substrate is deposited on the surface.
5	Removal of Unexposed Photoresist & mask		The mask is removed and the unexposed region of photoresist is dissolved by developing wafer using a chemical such as Trichloroethylene. A part of the photoresist layer is removed by treating the wafer with the basic or acidic solution.
6	Etching-Removal of SiO2 using acid etching		The SiO2 oxidation layer is removed, through the exposed area made by the removal of photoresist using hydrofluoric acid.
7	Removal of Whole Photoresist Layer		During the etching process, those portions of SiO2 which are protected by the photoresist layer are not affected. The entire photoresist mask is now stripped off with a chemical solvent (hot H2SO4).
8	Formation of N-well		By using ion implantation or diffusion process N-well is formed.The n-type impurities are diffused into the p-type substrate through the exposed region thus forming an N- well.
9	Removal of SiO2		Using the hydrofluoric acid, the remaining SiO2 is removed.
10	Deposition of polysilicon		Chemical Vapor Deposition (CVD) process is used to deposit a very thin layer of gate oxide.Polysilicon is deposited by using Chemical Deposition Process over a thin layer of gate oxide. This thin gate oxide under the Polysilicon layer prevents further doping under the gate region. Why use Polysilicon for fomation of the gate Because Polysilicon can withstand the high temperature greater than 80000c when a wafer is subjected to annealing methods for formation of source and drain. Why make the gate first before making source and drain? The misalignment of the gate of a CMOS transistor would lead to the unwanted capacitance which could harm circuit. So to prevent this “Self-aligned gate process” is preferred where gate regions are formed before the formation of source and drain using ion implantation.
11	Formation of Gate Region		Except the two regions required for formation of the gate for NMOS and PMOS transistors the remaining portion of Polysilicon is stripped off. Form the Gates.
12	Oxidation Process		An oxidation layer is deposited over the wafer which acts as a shield for further diffusion and metallization processes, have two small regions for the formation of the gate terminals of NMOS and PMOS.
13	Masking and Diffusion Formation of Gate Region		By using the masking process small gaps are made for the purpose of N-diffusion. The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for the formation of the terminals of NMOS.
14	Removal of Oxide		The oxide layer is stripped offThe remaining oxidation layer is stripped off
15	P-type Diffusion		Similar to the above N-diffusion process, the P-diffusion regions are diffused to form the terminals of the PMOS.
16	Thick field oxide		Step 16 – Laying of Thick Field oxide: Before forming the metal terminals a thick field oxide is laid out to form a protective layer for the regions of the wafer where no terminals are required.A thick-field oxide is formed in all regions except the terminals of the PMOS and NMOS.
17	Metallization		This step is used for the formation of metal terminals which can provide interconnections. Aluminum is spread on the whole wafer.
18	Removal of excess metal		The excess metal is removed from the wafer layer.
19	Terminals		The terminals of the PMOS and NMOS are made from respective gaps. In the gaps formed after removal of excess metal terminals are formed for the interconnections.
20	Assigning the Terminal Names		Names are assigned to the terminals of NMOS and PMOS transistors.

Reference

1. the-fabrication-process-of-cmos-transistor
2. The Fabrication Process of CMOS Transistor
3. Understanding About CMOS Fabrication Technology
4. SK海力士晶圆制造
5. STEP-by-step manufacturing of ULSI CMOS technologies
6. Fabrication Processes
7. CMOS Wafer Processing
8. Top view+3D view of LAYOUT DESIGN
9. CMOS processing-Silicon Labs芯科实验室
10. CMOS Process Flow (一)