HDLBits / fsm / Design a Moore FSM

Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).

code:

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    reg [1:0] state,next_state;
    
    //状态空间的定义
    parameter ls1=2'b00,ls21=2'b01,ls32=2'b10,ls3=2'b11;
    //组合逻辑描述状态之间转移的条件
    always@(*)begin
        case(s)
            3'b000:next_state = ls1;
            3'b001:next_state = ls21;
            3'b011:next_state = ls32;
            3'b111:next_state = ls3;
            default:next_state = ls1;
        endcase
    end
    //时序逻辑描述状态转移的过程
    always@(posedge clk)begin
        if(reset)
            state <= ls1;
        else
            state <= next_state;
    end
    //组合逻辑描述各个状态下的输出
    always@(*)begin
        case(state)
            ls1:{fr3,fr2,fr1} = 3'b111;
            ls21:{fr3,fr2,fr1} = 3'b011;
            ls32:{fr3,fr2,fr1} = 3'b001;
            ls3:{fr3,fr2,fr1} = 3'b000;
            default:{fr3,fr2,fr1} = 3'b111;
        endcase   
    end
    //时序逻辑判断输出dfr的值
    always@(posedge clk)begin
        if(reset)
            dfr <= 1'b1;
        else if(state < next_state)
            dfr <= 1'b0;
        else if(state > next_state)
            dfr <= 1'b1;
        else
            dfr <= dfr;
    end
        
endmodule