HDLBits /fsm / ps2 & ps2data

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    reg [1:0] state,next_state;
    //定义状态空间
	parameter byte1 = 2'b00,byte2=2'b01,byte3=2'b10,Done = 2'b11;

    //状态转移条件
    always@(*)begin
        case(state)
            byte1: next_state = in[3] ? byte2: byte1;
            byte2: next_state = byte3;
            byte3: next_state = Done;
            Done:  next_state = in[3]? byte2: byte1;
            default: next_state = byte1;
        endcase
    end

    // 状态转移过程
    always@(posedge clk or posedge reset)begin
        if(reset)
            state<= byte1;
        else
            state <= next_state;
    end

    // Output logic
    assign done = (state == Done);
endmodule

在前一道题的代码中最后加入out_bytes的输出就可以。

    always@(posedge clk)begin
        if(reset)
            out_bytes = 24'd0;
        else
            out_bytes = {out_bytes[15:0],in[7:0]};
    end