module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right); //
reg state, next_state;
//定义状态空间
parameter left = 1'b0,right = 1'b1;
//组合逻辑描述状态转移条件(state → next_state)
always @(*) begin
case(state)
left : next_state = bump_left ? right : left;
right : next_state =bump_right ? left : right;
endcase
end
//时序逻辑描述状态转移过程
always @(posedge clk, posedge areset) begin
if(areset)
state <= left;
else
state <= next_state;
end
//组合逻辑描述output
assign walk_left = (state == left);
assign walk_right = (state == right);
endmodule
HDLBits / fsm / lemmings1
最新推荐文章于 2024-09-06 11:18:02 发布