HDLBits / fsm / Lemmings2

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    //定义状态空间
    parameter left = 2'b00, right = 2'b01, left_fall = 2'b10, right_fall = 2'b11;
    reg [1:0] state,next_state;
    //组合逻辑描述状态转移条件
    always @(*)begin
        case(state)
            left:begin
                if(ground == 1'b0)
                    next_state = left_fall;
                else if (bump_left)
                    next_state = right;
                else
                    next_state = left;                  
            end
            right:begin
                if(ground == 1'b0)
                    next_state = right_fall;
                else if (bump_right)
                    next_state = left;
                else
                    next_state = right;                
            end
            left_fall:begin
               if(ground == 1'b0)
                   next_state = left_fall;
               else
                   next_state = left;                  
            end
            right_fall:begin
                if(ground == 1'b0)
                    next_state = right_fall;
                else 
                    next_state = right;                
            end                                
        endcase
    end
    //时序逻辑描述状态转移过程
    always@(posedge clk or posedge areset)begin
        if(areset)
            state <= left;
        else
            state <= next_state;
    end
    //组合逻辑描述状态的输出-示例1
  //always@(*)begin
  //    case(state)
  //       left: begin
  //           walk_left = 1;
  //           walk_right = 0;
  //       end
  //       right: begin
  //           walk_right = 1;
  //           walk_left = 0;
  //       end           
  //       default:begin
  //           walk_right = 0;
  //           walk_left = 0; 
  //       end   
  //    endcase
  //end
    
    //组合逻辑描述状态输出2
    assign walk_left = (state == left);
    assign walk_right = (state == right);
    
    //aaah的触发
    always@(posedge clk)begin
        if(ground ==0)
            aaah = 1'b1;
        else
            aaah = 1'b0;
    end
endmodule

1. 为什么逻辑状态输出只考虑left、right两种状态？因为left_fall，right_fall状态是在 由left、right状态在地面检测到离开的情况下触发的。在这种情况下，状态机会从 "left" 或 "right" 转移到相应的 "fall" 状态，然后在下一个时钟周期内再次将状态转移回 "left" 或 "right"。因此，在这个设计中，状态输出的关注点主要放在了最终的 "left" 和 "right" 状态上，而过渡状态 "left_fall" 和 "right_fall" 的状态输出并不需要单独考虑，因为它们不是最终的目标状态。
2. 输出用assign赋值语句更方便一些。