//快时钟域到慢时钟域的展宽打拍
module fast2slow_CDC(
input clk1,
input clk2,
input rst,
input pulse_clk1,
output pulse_syn_clk2
);
reg pulse_wide_clk2;
reg reg1_pulse_wide_clk2;
reg reg1_pulse_wide_clk1;
reg reg2_pulse_wide_clk1;
//生成脉冲展宽信号
reg pulse_wide_clk1;
always @ (posedge clk1 or posedge rst)
begin
if(rst)
begin
pulse_wide_clk1 <= 1'b0;
end
else if (pulse_clk1)
begin
pulse_wide_clk1 <= 1'b1;
end
else if (reg2_pulse_wide_clk1)
begin
pulse_wide_clk1 <= 1'b0;
end
else
begin
pulse_wide_clk1 <= pulse_wide_clk1;
end
end
//在目的时钟域内采样展宽后的信号
always @ (posedge clk2 or posedge rst)
begin
if(rst0)
begin
pulse_wide_clk2 <= 1'b0;
reg1_pulse_wide_clk2 <= 1'b0;
end
else
begin
pulse_wide_clk2 <= pulse_wide_clk1;
reg1_pulse_wide_clk2 <= pulse_wide_clk2;
end
end
//在源时钟域内同步目的时钟域内的展宽信号,以生成反馈信号
always @ (posedge clk1 or posedge rst)
begin
if(rst)
begin
reg1_pulse_wide_clk1 <= 1'b0;
reg2_pulse_wide_clk1 <= 1'b0;
end
else
begin
reg1_pulse_wide_clk1 <= reg1_pulse_wide_clk2;
reg2_pulse_wide_clk1 <= reg1_pulse_wide_clk1;
end
end
assign pulse_syn_clk2 = reg1_pulse_wide_clk2;
endmodule
总结:
1.首先是脉冲展宽(快时钟域下脉冲到来拉高,快时钟域下反馈信号到来拉低)。
2.脉冲展宽在慢时钟域下打两拍,结果作为同步输出。
3.同步输出信号在快时钟域下打两拍,结果作为反馈信号。