HDLBits刷题之2.1.7----Verilog Language----Basics----Declaring wires.

7.Declaring wires

Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs.

题目大意是需要声明几根线来实现以上电路结构，对于上图，绿色部分的线才是我们应该去声明的wire类型，代码如下所示：

module top_module (
	input a,
	input b,
	input c,
	input d,
	output out,
	output out_n );
	
	wire w1, w2;		
	assign w1 = a & b;	
	assign w2 = c & d;	
	assign out = w1 | w2;	

	assign out_n = ~out;	
	
endmodule