HDLBits刷题之2.2.7----Verilog Language----Vectors----Vector reversal 1

7.Vector reversal 1

Given an 8-bit input vector [7:0], reverse its bit ordering.

题目意思是给定一个8位输入，将这8位输入翻转输出，代码如下所示：

module top_module (
	input [7:0] in,
	output [7:0] out
);
	
	assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
endmodule