源程序
module DFF(
input clk,
input rst_n,
input en,
input d,
output reg q
);
always @(posedge clk, negedge rst_n)
begin
if(rst_n==0)
q <= 1'b0;
源程序
module DFF(
input clk,
input rst_n,
input en,
input d,
output reg q
);
always @(posedge clk, negedge rst_n)
begin
if(rst_n==0)
q <= 1'b0;