VHDL 设计单口RAM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity M_Ram is
    port
    (
    ----------------------------------------------------------------------------
    --rest and system clock
    ----------------------------------------------------------------------------
        CpSl_SysClk_i                   : in std_logic;                         -- system clock
        CpSl_Rst_i                      : in std_logic;                         -- rest
        
    ----------------------------------------------------------------------------
    --input addr and enable signal and ram_data
    ----------------------------------------------------------------------------
        CpSl_WEn_i                      : in std_logic;                         -- write enable
        CpSl_REn_i                      : in std_logic;                         -- read enable
        CpSl_CsEn_i                     : in std_logic;                         -- ram enable
        CpSv_WAddr_i                    : in std_logic_vector(7 downto 0);      -- write address
        CpSv_RAddr_i                    : in std_logic_vector(7 downto 0);      -- read address
        CpSv_RamData_i                  : in std_logic_vector(7 downto 0);      -- ram receive data
        
    ----------------------------------------------------------------------------
    --output ram data and ram data valid signal 
    ----------------------------------------------------------------------------
        CpSl_DataVld_o                  : out std_logic;                        -- read ram data valid
        CpSv_RamData_o                  : out std_logic_vector(7 downto 0)      -- read ram data
    );
end M_Ram;

architecture Behavioral of M_Ram is

--------------------------------------------------------------------------------
--constant declaration
--------------------------------------------------------------------------------
    type Ram_type is array (9 downto 0) of std_logic_vector (7 downto 0);       --Defining ram types 
    signal Ram_array                    : Ram_type;                             --create ram memory with a width of 8 and depth of 10
    
begin
    
    ----------------------------------------------------------------------------
    --data writing to ram 
    ----------------------------------------------------------------------------
    process(CpSl_SysClk_i,CpSl_Rst_i) begin
        if(CpSl_Rst_i = '0') then
            for i IN 0 TO 9 Loop
                Ram_array(conv_integer(i)) <= x"00";
            end LOOP;
        elsif rising_edge(CpSl_SysClk_i) then
            if(CpSl_WEn_i = '1' and CpSl_CsEn_i = '1') then
                Ram_array(conv_integer(CpSv_WAddr_i)) <= CpSv_RamData_i;
            else --hold
            end if;
        end if;
    end process;
    
    ----------------------------------------------------------------------------
    --reading ram data
    ----------------------------------------------------------------------------
    process(CpSl_SysClk_i,CpSl_Rst_i) begin
        if(CpSl_Rst_i = '0') then
            CpSv_RamData_o <= (others => '0');
        elsif rising_edge(CpSl_SysClk_i) then
            if(CpSl_REn_i = '1' and CpSl_CsEn_i = '1' and CpSl_WEn_i = '0') then
                CpSv_RamData_o <= Ram_array(conv_integer(CpSv_RAddr_i));
            else 
                CpSv_RamData_o <= (others => '0');
            end if;
        end if;
    end process;
    
    ----------------------------------------------------------------------------
    --read ram data valid
    ----------------------------------------------------------------------------
    process(CpSl_SysClk_i,CpSl_Rst_i) begin
        if(CpSl_Rst_i = '0') then
            CpSl_DataVld_o <= '0';
        elsif rising_edge(CpSl_SysClk_i) then
            if(CpSl_REn_i = '1' and CpSl_CsEn_i = '1' and CpSl_WEn_i = '0') then
                CpSl_DataVld_o <= '1';
            else
                CpSl_DataVld_o <= '0';
            end if;
        end if;
    end process;


end Behavioral;

testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity M_Ram_tb is
end M_Ram_tb;

architecture Behavioral of M_Ram_tb is

    component M_Ram
    port
    (
    ----------------------------------------------------------------------------
    --rest and system clock
    ----------------------------------------------------------------------------
        CpSl_SysClk_i                   : in std_logic;                         -- system clock
        CpSl_Rst_i                      : in std_logic;                         -- rest
        
    ----------------------------------------------------------------------------
    --input addr and enable signal and ram_data
    ----------------------------------------------------------------------------
        CpSl_WEn_i                      : in std_logic;                         -- write enable
        CpSl_REn_i                      : in std_logic;                         -- read enable
        CpSl_CsEn_i                     : in std_logic;                         -- ram enable
        CpSv_WAddr_i                    : in std_logic_vector(7 downto 0);      -- write address
        CpSv_RAddr_i                    : in std_logic_vector(7 downto 0);      -- read address
        CpSv_RamData_i                  : in std_logic_vector(7 downto 0);      -- ram receive data
        
    ----------------------------------------------------------------------------
    --output ram data and ram data valid signal 
    ----------------------------------------------------------------------------
        CpSl_DataVld_o                  : out std_logic;                        -- read ram data valid
        CpSv_RamData_o                  : out std_logic_vector(7 downto 0)      -- read ram data
    );
    end component;
    
    --input
    signal CpSl_SysClk_i                : std_logic := '0';
    signal CpSl_Rst_i                   : std_logic := '0';
    signal CpSl_WEn_i                   : std_logic;
    signal CpSl_REn_i                   : std_logic;
    signal CpSl_CsEn_i                  : std_logic := '1';
    signal CpSv_WAddr_i                 : std_logic_vector(7 downto 0);
    signal CpSv_RAddr_i                 : std_logic_vector(7 downto 0);
    signal CpSv_RamData_i               : std_logic_vector(7 downto 0):= "01010110";
                                          
    --output                              
    signal CpSl_DataVld_o               : std_logic := '0';
    signal CpSv_RamData_o               : std_logic_vector(7 downto 0);
    signal PrSv_Cnt_s                   : std_logic_vector(3 downto 0);
    
    constant clk_period                 : time := 10ns;
begin

    --gen system clock
    clk_gen: process
    begin
            CpSl_SysClk_i <= '0';
        wait for clk_period /2;
            CpSl_SysClk_i <= '1';
        wait for clk_period /2;
    end process;
    
    --gen rest signal
    rst_gen: process
    begin       
        -- hold reset state for 100 ns.
        wait for 100ns; 
            CpSl_Rst_i <= '1'; 
        wait;
    end process;
    
    --gen data
    process(CpSl_SysClk_i) begin
        if rising_edge(CpSl_SysClk_i) then
            CpSv_RamData_i <= CpSv_RamData_i(6 downto 0) & CpSv_RamData_i(7);
        end if;
    end process;
    
    -- counter Calculates write and read cycles
     process(CpSl_SysClk_i,CpSl_Rst_i) begin
        if(CpSl_Rst_i = '0') then
            PrSv_Cnt_s <= (others => '0');
        elsif rising_edge(CpSl_SysClk_i) then
            if(PrSv_Cnt_s = "1111") then
                PrSv_Cnt_s <= (others => '0');
            else
                PrSv_Cnt_s <= PrSv_Cnt_s + '1';
            end if;
        end if;
    end process;
    
    --gen write enable signal
    process(CpSl_SysClk_i,CpSl_Rst_i) begin
        if(CpSl_Rst_i = '0') then
            CpSl_WEn_i <= '0';
        elsif rising_edge(CpSl_SysClk_i) then
            if(PrSv_Cnt_s < "1000") then
                CpSl_WEn_i <= '1';
            else
                CpSl_WEn_i <= '0';
            end if;
        end if;
    end process;
    
    -- gen Write address
    process(CpSl_SysClk_i,CpSl_Rst_i) begin
        if(CpSl_Rst_i = '0') then
            CpSv_WAddr_i <= (others => '0');
        elsif rising_edge(CpSl_SysClk_i) then
            if(PrSv_Cnt_s < "1000") then
                CpSv_WAddr_i <= CpSv_WAddr_i + '1';
            else
                CpSv_WAddr_i <= (others => '0');
            end if;
        end if;
    end process;
    
    --gen read enable signal
    process(CpSl_SysClk_i,CpSl_Rst_i) begin
        if(CpSl_Rst_i = '0') then
            CpSl_REn_i <= '0';
        elsif rising_edge(CpSl_SysClk_i) then
            if(PrSv_Cnt_s > "0111") then
                CpSl_REn_i <= '1';
            else
                CpSl_REn_i <= '0';
            end if;
        end if;
    end process;

    --gen read address
    process(CpSl_SysClk_i,CpSl_Rst_i) begin
        if(CpSl_Rst_i = '0') then
            CpSv_RAddr_i <= (others => '0');
        elsif rising_edge(CpSl_SysClk_i) then
            if(PrSv_Cnt_s > "0111") then
                CpSv_RAddr_i <= CpSv_RAddr_i + '1';
            else
                CpSv_RAddr_i <= (others => '0');
            end if;
        end if;
    end process;

    uut:M_Ram
    port map(
        CpSl_SysClk_i                   => CpSl_SysClk_i ,                      
        CpSl_Rst_i                      => CpSl_Rst_i    ,                      
        CpSl_WEn_i                      => CpSl_WEn_i    ,                      
        CpSl_REn_i                      => CpSl_REn_i    ,                      
        CpSl_CsEn_i                     => CpSl_CsEn_i ,                        
        CpSv_WAddr_i                    => CpSv_WAddr_i ,                       
        CpSv_RAddr_i                    => CpSv_RAddr_i     ,                   
        CpSv_RamData_i                  => CpSv_RamData_i,                       
        CpSl_DataVld_o                  => CpSl_DataVld_o,                       
        CpSv_RamData_o                  => CpSv_RamData_o                       

    );
end Behavioral;