【RTL】verilog表达式的位宽计算

1. Verilog表达式的位宽计算

可以简单查这个表是否会自动做位宽扩展
L(i)的意思是i的位宽

Expression	Bit length	Comments
unsized constant	32 bits	Self-determined
sized constant	as specified	Self-determined
i + j	max(L(i),L(j))	Context-determined
i – j	max(L(i),L(j))	Context-determined
i * j	max(L(i),L(j))	Context-determined
i / j	max(L(i),L(j))	Context-determined
i % j	max(L(i),L(j))	Context-determined
i & j	max(L(i),L(j))	Context-determined
i | j	max(L(i),L(j))	Context-determined
i ^ j	max(L(i),L(j))	Context-determined
i ^~ j	max(L(i),L(j))	Context-determined
~i	L(i)	Context-determined
i == j	1 bit	Self-determined
i !== j	1 bit	Self-determined
i && j	1 bit	Self-determined
i || j	1 bit	Self-determined
i > j	1 bit	Self-determined
i >= j	1 bit	Self-determined
i < j	1 bit	Self-determined
i <= j	1 bit	Self-determined
&i	1 bit	Self-determined
|i	1 bit	Self-determined
^i	1 bit	Self-determined
~&i	1 bit	Self-determined
~|i	1 bit	Self-determined
~^i	1 bit	Self-determined
i >> j	L(i)	j is self-determined
{i{j}}	i*L(j)	j is self-determined
i << j	L(i)	j is self-determined
{i,…,j}	L(i)+…+L(j)	Self-determined
{i {j,…,k}}	i*(L(j)+…+L(k))	Self-determined
i ? j : k	Max(L(j),L(k))	i is self-determined

2. 概念 （IEEE Std 1364-2001）

A self-determined expression is one where the bit length of the expression is solely determined by the
expression itself for example, an expression representing a delay value.

A context-determined expression is one where the bit length of the expression is determined by the bit length
of the expression and by the fact that it is part of another expression. For example, the bit size of the righthand side expression of an assignment depends on itself and the size of the left-hand side.

简单来说，
self-determined就是固定的、确定的
context-determined就是根据其他表达式会变的

verilog 2001虽然提了这个概念，但是没有过多解释哪些表达式属于context-determined
不过于纠结概念，直接看上表的结果就行了。

3. Example

表达式位宽不匹配时，不注意verilog位宽自动扩展规则，容易导致非预期的结果

//Example 1
wire a[7:0];
wire b[7:0];
wire c[3:0];
assgin b = 8'h0;
assign c = 4'hf;
assign a = b + ~c;

//reselt : a = 8'h0    —— no
//result : a = 8'hf0   —— yes

计算方式：
1.先看加法，因为b位宽为8，所以后面表达式位宽扩展{4’b0,c}变成
a = 8’h0; + ~{4’h0,c};
2.再看取反
a = 8’h0 + {4’hf,4’h0};

//Example 2
if ( ((1’b1 << 15) >> 15) == 1’b0 )
//This expression is ALWAYS true.
if ( (((1’b1 << 15) >> 15) | 20’b0) == 1’b0 )
//This expression is NEVER true.

这个是抄过来的例子，也是 | 20’b0 对位移表达式的位宽扩展了，结合表格自行理解。

4. REF

https://book.huihoo.com/pdf/crafting-a-chip-a-practical-guide-to-the-uofu-vlsi-cad-flow/synopsys/hdlcv_4.pdf
IEEE Standard Verilog® Hardware Description Language (IEEE Std 1364-2001)