CSDN尊敬的工作人员和各位专家:
本人将自己亲自调试的基于xilinx ultra96开发板利用最新软件Vitis的第一个例程Hello写成文档,由于CSDN上无法上传word文档,作者本人时间有限,没有时间转换格式,只好上传到作者本人的Github, 请各位移步下载,请CSDN工作人员见谅!
GitHubDoc/Hello World on the Ultra96 Using Vitis.docx at master · johnwang9/GitHubDoc https://github.com/johnwang9/GitHubDoc/blob/master/Hello%20World%20on%20the%20Ultra96%20Using%20Vitis.docx
vitis软件约占空间
john@john-virtual-machine:/mnt/hgfs/xilinx/Xilinx_Vitis_2019.2_1106_2127/Xilinx_Vitis_2019.2_1106_2127$ ./xsetup
#2037年之前的任何Vivado版本(包括HLS、AccelDSP、System Generator、软硬CPU、SOC、嵌入式Linux、重配置等等功能)都是永久使用。使用本license文件时要改名,文件名不能有汉字和空格。复制保存为.lic文件即可用
INCREMENT VIVADO_HLS xilinxd 2037.05 permanent uncounted AF3E86892AA2
VENDOR_STRING=License_Type:Bought HOSTID=ANY ISSUER=“Xilinx
Inc” START=19-May-2016 TS_OK
INCREMENT Vivado_System_Edition xilinxd 2037.05 permanent uncounted
A1074C37F742 VENDOR_STRING=License_Type:Bought HOSTID=ANY
ISSUER=“Xilinx Inc” START=19-May-2016 TS_OK
PACKAGE Vivado_System_Edition xilinxd 2037.05 DFF4A65E0A68
COMPONENTS=“ISIM ChipScopePro_SIOTK PlanAhead ChipscopePro XPS
ISE HLS_Synthesis AccelDSP Vivado Rodin_Synthesis
Rodin_Implementation Rodin_SystemBuilder
PartialReconfiguration AUTOESL_FLOW AUTOESL_CC AUTOESL_OPT
AUTOESL_SC AUTOESL_XILINX petalinux_arch_ppc
petalinux_arch_microblaze petalinux_arch_zynq ap_sdsoc SDK
SysGen Simulation Implementation Analyzer HLS Synthesis
VIVADO_HLS” OPTIONS=SUITE
john@john-virtual-machine:~/Vitis2019.2/Vivado/2019.2$ echo ‘source /home/john/Vitis2019.2/Vivado/2019.2/settings64.sh’ >> ~/.bashrc
john@john-virtual-machine:~/Vitis2019.2/Vivado/2019.2$ echo ‘source /home/john/Vitis2019.2/Vitis/2019.2/settings64.sh’ >> ~/.bashrc