JTAG refers to IEEE Std 1149.1-2013.
It is a standard that defines
test logic that can be included in an integrated circuit
to test the interconnections between integrated circuits, test the integrated circuit itself,
and observe or modify circuit activity during the components normal operation.
This specification uses the latter functionality.// observe ...
The JTAG standard defines a Test Access Port(TAP) that can be used to read and write a few custom registers,
which can be used to communicate with debug hardware in a component.
如今 JTAG 接口的连接有两种标准,即 14 针接口和 20 针接口
准的JTAG接口是4线:TMS、TCK、TDI、TDO,分别为模式选择、时钟、数据输入和数据输出线。
TMS为测试模式选择,TMS用来设置JTAG接口处于某种特定的测试模式;上升沿锁存
TCK为测试时钟输入;
TDI为测试数据输入,数据通过TDI引脚输入JTAG接口;
TDO为测试数据输出,数据通过TDO引脚从JTAG接口输出;
TRST为测试复位,输入引脚,低电平有效。
MCU的JTAG电路在TCK的上升沿采样TDI的信号,在下降沿在TDO输出数据
时钟TCK的每个上升沿锁存数据,上文所述的TAP控制器有16个不同的状态,TMS的值控制着当前的状态变化。上电伊始,TAP处于TEST_LOGIC/RESET状态,然后每个TCK上升沿锁存到的TMS值相应的决定着TAP控制器的下一个状态。后缀_IR和_DR分别指指令寄存器和数据寄存器。
The Test Access Port
The JTAG Test Access Port(TAP) contains four pins that drive the circuit blocks and control the operations specified. The TAP facilitates the serial loading and unloading of instructions and data. The four pins of the TAP are: TMS, TCK, TDI and TDO. The function of each TAP pin is as follows:
TCK - this pin is the JTAG test clock. It sequences the TAP controller as well as all of the JTAG registers.
TMS - this pin is the mode input signal to the TAP Controller. The TAP controller is a 16-state FSM that provides the control logic for JTAG. The state of TMS at the rising edge of TCK determines the sequence of states for the TAP controller. TMS has an internal pull-up resistor on it to provide a logic 1 to the system if the pin is not driven.
TDI - this pin is the serial data input to all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register is fed by TDI for a specific operation. TDI has an internal pull-up resistor on it to provide a logic 1 to the system if the pin is not driven. TDI is sampled into the JTAG registers on the rising edge of TCK.
TDO - this pin is the serial data output for all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register feeds TDO for a specific operation. Only one register(instruction or data) is allowed to be the active connection between TDI and TDO for any given operation. TDO changes state on the
falling edge of TCK and is only active during the shifting of data through the device. This pin is three-stated at all other times.
jtag标准-1993jtag标准-2013jtag标准官方地址IEEE 1149.1a-1993 - Supplement to Standard Test Access Port and Boundary-Scan Architecture (1149.1)概要哪里有现在多数的高级器件都支持JTAG协议,如DSP、FPGA器件等作用芯片内部测试。独立于cpu进...