【FPGA】【Verilog】【基础模块】排序

冒泡法：

    使用task实现:

module sort4(ra,rb,rc,rd,a,b,c,d);
	output [3:0] ra,rb,rc,rd;
	input [3:0] a,b,c,d;

	reg [3:0] ra,rb,rc,rd;
	reg [3:0] va,vb,vc,vd;

always @(a or b or c or d)
	begin 
			{va,vb,vc,vd} = {a,b,c,d};
			sort2(va,vc);
			sort2(vb,vd);
			sort2(va,vb);
			sort2(vc,vd);
			sort2(vb,vc);
			{ra,rb,rc,rd} = {va,vb,vc,vd};
	end

	task sort2;
		inout [3:0] x,y;
		reg [3:0] temp;
		if (x > y)
			begin 
				temp = x;
				x = y;
				y = temp;
			end
	endtask
endmodule 

            testbench:

`timescale 1 ns / 100 ps
`include"C:/Users/ydxqwer/Desktop/Bush_book_FPGA/round1/sort4.v"

module sort4_vlg_tst();
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
reg [3:0] d;                                              
wire [3:0]  ra;
wire [3:0]  rb;
wire [3:0]  rc;
wire [3:0]  rd;


initial                                                
begin                                                  
	 a = 0;
	 b = 0; 
	 c = 0; 
	 d = 0;
	 
	 repeat(5)
	 begin
	 #100 a ={$random}%15;
			b ={$random}%15;
			c ={$random}%15;
			d ={$random}%15;
	 end   
	 
	#100 $stop;
end
	sort4 sort4(.a(a),.b(b),.c(c),.d(d), .ra(ra),.rb(rb),.rc(rc),.rd(rd));
	
endmodule