不用寄存器可以减少延迟
module MUX4T1_32(
input [1:0]s,
input [31:0]I0, I1, I2, I3,
output [31:0]o
);
wire s0 = s == 2'b00;
wire s1 = s == 2'b01;
wire s2 = s == 2'b10;
wire s3 = s == 2'b11;
assign o = {32{s0}} & I0 |
{32{s1}} & I1 |
{32{s2}} & I2 |
{32{s3}} & I3 ;
endmodule
使用寄存器的MUX:
module MUX4T1_32( input [1:0]s,
input [31:0]I0,
input [31:0]I1,
input [31:0]I2,
input [31:0]I3,
output reg[31:0]o
);
always@*
case(s)
2'b00: o = I0;
2'b01: o = I1;
2'b10: o = I2;
2'b11: o = I3;
endcase
endmodule