module sync_fifo
#(parameter N=32)
(
input clk,
input rst_n,
input wr,
input rd,
input [N-1:0] wdata,
output [N-1:0] rdata,
output empty,
output full
);
reg [N-1:0] shift_reg [N-1:0];
wire wen=wr & ~full;
wire rdn=rd & ~empty;
assign empty=(|data_cnt);
assign full =(&data_cnt);
reg [N-1:0] rdata_r;
always @(posedge clk, negedge rst_n) begin
if(!rst_n) begin
for(int i=0;i<N;i=i+1)
shift_reg[i]<='b0;
end
else if(wen) begin
shift_reg[0]<=wdata;
for(int i=1;i<N-1;i=i+1)
shift_reg[i]<=shift_reg[[i-1];
end
end
always @(posedge clk ,negedge rst_n) begin
if(!rst_n)
rdata_r<='b0;
else if(wen) begin
rdata_r<=shift_regs[data_cnt-1];
end
end
always @(posedge clk ,negedge rst_n) begin
if(!rst_n)
data_cnt<='b0;
else begin
case(ren,wen)
2'b01:data_cnt<=data_cnt+1'b1;
2'b10:data_cnt<=data_cnt-1'b1;
default:data_cnt<=data_cnt;
endcase
end
end
assign rdata=rdata_r
endmodule
05-26
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08-09
7752
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08-23
2856
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