文章目录
- 1.逻辑综合
- 1.1 查看CPU核心数
- 1.2 启动DC
- 1.3 set_svf STOTO.svf(formality用于做逻辑等价性验证)
- 1.4 read、link、check design
- 1.5 source and check the timing constraints
- 1.6 source STOTO.pcon(物理约束/物理综合)
- 1.7 report_clock
- 1.8. 设置spec1、2
- 1.9 设置 spec3
- 1.10 spec4
- 1.11 spec5
- 1.12 设置 spec6
- 1.13 保存为unmapped/xxx.ddc
- 1.14 enable multi-core optimization
- 1.15 Compile
- 1.16 list licence
- 1.17 report_hierarchy -noleaf
- 1.18 Generate a constraints report and timing report
- 1.19 保存mapped/ddc
- 1.20 Stop recording design changes in the SVF file for Formality
- 1.21 get_cells -hier *r_REG*_S*
- 1.22 report_cell -nosplit I_MIDDLE/I_PIPELINE
- 1.23 get_cells -hier *z_reg*
- 1.24 report_timing -from I_MIDDLE/I_PIPELINE/z_reg*/*
- 1.25 get_cells -hier R_*
- 1.26 report_cell -nosplit I_IN
- 1.27 get_cells I_IN/*_reg*
- 2. DC LAB5基础知识
- 3. Formal Verification
1.逻辑综合
1.1 查看CPU核心数
1.2 启动DC
dc_shell-t -64bit -topo
1.3 set_svf STOTO.svf(formality用于做逻辑等价性验证)
1.4 read、link、check design
1.4.1 read_verilog STOTO.v
1.4.2 current_design STOTO
1.4.3 link
1.4.4 check design
1.4.5 list of designs and libraries in memory
1.5 source and check the timing constraints
1.5.1 source STOTO.con
1.5.2 check_timing
对于setup只设置了max delay,min delay不用管,这里可以不管warning
1.6 source STOTO.pcon(物理约束/物理综合)
1.7 report_clock
1.8. 设置spec1、2
group_path -name clk -critical 0.21 -weight 5
group_path -name INPUTS -from [all_inputs]
group_path -name OUTPUTS -to [all_output]
group_path -name COMBO -from [all_inputs] -to [all_output]
1.8.1 report_path_group
1.9 设置 spec3
#PIPELINE INPUT依然是group
#
set_ungroup [get_designs "PIPELINE INPUT"] false
1.9.1 get_attribute [get_designs “PIPELINE INPUT”] ungroup
# Verify that the "ungroup" attribute was correctly applied to the designs.
# Expect this command to return "false false".
# If you get message "Attribute 'ungroup' does not exist on design .." then apply the
# set_ungroup command. If applied to the wrong design, remove with
# remove_attribute [get_designs "XYX ABC"] ungroup.
# Note: Do not use "set_ungroup .. true" as this will force the designs to be ungrouped
# during compile, no matter what, instead of allowing auto-ungroup to make a possibly
# smarter decision.
1.10 spec4
# Retime the PIPELINE block
set_optimize_registers true -design PIPELINE
1.11 spec5
# Do NOT retime the DONT_PIPELINE block as per spec
set_dont_retime [get_cells I_MIDDLE/I_DONT_PIPELINE] true
# Check that the dont_retime attribute is correctly applied
get_attribute [get_cells I_MIDDLE/I_DONT_PIPELINE] dont_retime
1.12 设置 spec6
# While retiming the PIPELINE block, make sure its output registers are
# not mopved
set_dont_retime [get_cells I_MIDDLE/I_PIPELINE/z_reg*] true
# Check that the dont_retime attribute is correctly applied
get_attribute [get_cells I_MIDDLE/I_PIPELINE/z_reg*] dont_retime
1.13 保存为unmapped/xxx.ddc
# Save the un-compiled design
#
write -f ddc -hier -out unmapped/STOTO.ddc
1.14 enable multi-core optimization
# Based on the available resources (Number of CPU cores and licenses)
# specify and report multi core optimization setting
set_host_options -max_cores 3
report_host_options
1.15 Compile
# Compile the design. Since the design is timing-critical, and is expected to
# have scan-chains inserted, include the "-scan" and the "-timing" options.
# Enable adaptive retiming to retime the non-pipelined parts of the design
compile_ultra -scan -timing -retime
- compile_ultra -scan -timing -retime
- redirect -file compile.log {compile_ultra -scan -timing -retime}, 这里使用的重定位的命令redirect,意思是将后面{}中命令的执行结果保存到文件中, 不加-tee 表示不在当前终端显示
1.16 list licence
# Examine the number and names of License Features used
list_licenses
1.17 report_hierarchy -noleaf
# Find out what blocks have been auto-ungrouped: MIDDLE, OUTPUT, DONT_PIPELINE, GLUE, ARITH and RANDOM;
# The only remaining designs in the hierarchy should be STOTO, PIPELINE, and INPUT.
# If you get different results, verify that you correctly
# specified the "set_ungroup" attribute.
#
report_hierarchy -noleaf
1.18 Generate a constraints report and timing report
# Generate a constraints report (remember to include "-all").
# Expect to see max-delay violations in the INPUTS and COMBO groups.
#
# We should not be too concerned about these max-dealy violations because
# the Design Specification warned us that the I/O constraints are "estimates and have
# been conservatively constrained".
#
# You SHOULD NOT see any max-delay violations in the "clk" group!
#
# Notice too that cell names, by default, retain their hierarchical name even though
# their parent block(s) may have been ungrouped (e.g. I_MIDDLE/I_DONT_PIPELINE/I_RANDOM/int1_reg*).
#
redirect -tee -file rc_compile_ultra.rpt {report_constraint -all}
redirect -tee -file rt_compile_ultra.rpt {report_timing}
1.19 保存mapped/ddc
# Save the design
#
write -f ddc -hier -out mapped/STOTO.ddc
1.20 Stop recording design changes in the SVF file for Formality
# Stop recording SVF changes
#
set_svf -off
1.21 get_cells -hier r_REG_S*
# Verify that register retiming moved registers in the PIPELINE design:
# Since this command returns specific cell names this proves that registers retiming did
# in fact move some registers. Since every single cell name starts with "I_MIDDLE/I_PIPELINE"
# you can conclude that only PIPELINE registers were moved. Lastly, since all the register
# cells end with "S1" we can conclude that only z1_reg*, the first stage registers, were moved.
# The latter can be further verified with additional checks.
#
get_cells -hier *r_REG*_S*
1.22 report_cell -nosplit I_MIDDLE/I_PIPELINE
# Verify that the instance name I_MIDDLE/I_PIPELINE corresponds to the
# design or "reference" name PIPELINE:
#
report_cell -nosplit I_MIDDLE/I_PIPELINE
1.23 get_cells -hier z_reg
# Verify that the second stage "z_reg" registers have not been moved
#
get_cells -hier *z_reg*
1.24 report_timing -from I_MIDDLE/I_PIPELINE/z_reg*/*
# You can also show that the output of PIPELINE is regsitered with:
report_timing -from I_MIDDLE/I_PIPELINE/z_reg*/*
1.25 get_cells -hier R_*
# Verify that registers in INPUTS were moved by adaptive retiming:
get_cells -hier R_*
1.26 report_cell -nosplit I_IN
# Verify that the instance name I_IN corresponds to the
# design or "reference" name INPUT:
#
report_cell -nosplit I_IN
1.27 get_cells I_IN/_reg
# Verify that not ALL the registers in INPUT were affected or moved by adaptive retiming:
#
get_cells I_IN/*_reg*
2. DC LAB5基础知识
2.1 Open aLayoutWindow from the DesignVision GUI(物理综合)
物理综合需要读取floorplan的信息,综合工具通过这些floorplan信息就知道了设计大小、port和macro的摆放位置,基于此去做物理综合,其时序会更加贴近实际的情况,得到的网表质量也更高一点
2.2 设置的hard blockage
hard: 是约束最严格的blockage,该区域范围内,place,legalize, optimize,CTS等任何阶段都不能摆放instance。
soft:该区域内,在placement阶段不允许摆放instance,但是在legalize,optimize阶段时允许摆放instance的
partial: 如果要使用partial blockage,首先要人为设计一个阻碍百分比值。在该区域内,工具会block住阻碍值的instance。如果设定了block百分比值是40%,就说明该区域至少会block40%的instance,也就是说该区域最多允许摆放60%的instance. 值得注意的是partial blockage也是只在placement阶段起作用,在legalize,optimize阶段时都不起作用。
hard_macro: 该区域内不允许摆放hard macro,在自动macro placement阶段工具不会摆放macro在该区域。
2.3 port
2.4 standard cell
2.5 standard cell overlap
- You may notice that several standard cells overlap. This is because DC-Topo uses a “coarse placement” algorithm for quicker placement, and does not perform placement “legalization”. Coarse placement is good enough for purposes of estimating the interconnect or net parasitic R/C’s.
3. Formal Verification
3.1 fm_shell
3.2 source -echo ./scripts/fm.tcl