Fsm1s

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations

    reg present_state, next_state;
    parameter B=1,A=0;

    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            present_state=B;
        end else begin
            case (present_state)
                // Fill in state transition logic
                B: next_state=(in)?B:A;
                A: next_state=(in)?A:B;
            endcase
		
            // State flip-flops
            present_state = next_state;   
		end
        case (present_state)
            // Fill in output logic
            A: out=0;
            B: out=1;
         endcase
        
    end

endmodule