HDLbits--Fsm2/Fsm2s

 Fsm2

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            ON:
                begin
                    next_state<= k?OFF:ON;
                end
            OFF:
                begin
                    next_state<=j?ON:OFF;
                end
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state<=OFF;
        else
            state<=next_state;
    end

    // Output logic
    // assign out = (state == ...);
    assign out = (state==ON)?1:0;

endmodule

Fsm2s

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            ON:
                begin
                    next_state<= k?OFF:ON;
                end
            OFF:
                begin
                    next_state<=j?ON:OFF;
                end
        endcase

    end

    always @(posedge clk) begin
        // State flip-flops with synchronous reset
        if(reset)
            state<=OFF;
        else
            state<=next_state;

    end

    // Output logic
    // assign out = (state == ...);
    assign out = (state==ON)?1:0;

endmodule