module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //
parameter idel=0,s1=1,s2=2,s3=3;
reg [1:0] state,next_state;
reg [7:0] in1,in2,in3;
// FSM from fsm_ps2
always@(*)
begin
case(state)
idel:
next_state<=in[3]?s1:idel;
s1:begin
next_state<=s2;
end
s2:begin
next_state<=s3;
end
s3:begin
next_state<=in[3]?s1:idel;
end
endcase
end
always@(posedge clk)
begin
if(reset)
state<=idel;
else
state<=next_state;
end
// New: Datapath to store incoming bytes.
always@(posedge clk)
begin
if(next_state==s1)
in1<=in;
if(next_state==s2)
in2<=in;
if(next_state==s3)
in3<=in;
end
assign done =(state==s3);
assign out_bytes=(done)?{in1,in2,in3}:0;
endmodule
第一次错了 把42 44 46行的state改成next-state后正确。