HDLbits---Circuits---Sequential Logic---Counters

1.count15

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);
    always@(posedge clk) begin
        if(reset)
            q<=0; 
        else 
            if(q==4'b1111)
                q<=0;
        else 
            q<=q+1;
    end
endmodule

2.Count10

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
    always@(posedge clk) begin
        if(reset)
            q<=0; 
        else if(q=='d9) begin
            q<=0; end
        else  begin
            q<=q+1; end
    end
endmodule

3.Count1to10

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    always@(posedge clk) begin
        if(reset)
            q<='d1;
        else if(q=='d10)
            q<='d1;
        else 
            q<=q+1;
    end
endmodule

4.countslow

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    always@(posedge clk) begin
        if(reset)
            q<=0;
        else  begin
            if(slowena) begin
                if(q=='d9)
                    q<=0;
                else 
                    q<=q+1;
            end
        else
            q<=q;
        end
    end
    
endmodule

5.exams/ece241_2014_q7a

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); 
//其实我觉得我这里的上面提示是有一点问题的这里的c_其实是用在我整个模块化里面的
   assign c_d=c_load?4'd1:4'd0;
    assign c_load=reset|((Q=='d12)&&(c_enable=='d1));
    assign c_enable=enable;
    count4 U1(clk,c_enable,c_load,c_d,Q);  
endmodule

6.exams/ece241_2014_q7b

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    wire [3:0] a,b,c;
    assign c_enable[0]=1;
    assign c_enable[1]=(a=='d9)?1:0;
    assign c_enable[2]=(a=='d9&&b=='d9)?1:0;
    assign OneHertz={a=='d9&&b=='d9&&c=='d9};
    bcdcount U1(clk,reset,c_enable[0],a);
    bcdcount U2(clk,reset,c_enable[1],b);
    bcdcount U3(clk,reset,c_enable[2],c);
endmodule

7.countbcd

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
    wire[3:0] q0,q1,q2,q3;
    assign q[3:0]=q0;
    assign q[7:4]=q1;
    assign q[11:8]=q2;
    assign q[15:12]=q3;
    assign ena[1]={q0=='d9};
    assign ena[2]={q0=='d9&&q1=='d9};
    assign ena[3]={q0=='d9&&q1=='d9&&q2=='d9};
    always@(posedge clk) begin
        if(reset)
            q0<=0;
        else if(q0=='d9)
            q0<=0;
        else
            q0<=q0+1;
    end
    always@(posedge clk) begin
        if(reset)
            q1<=0;
        else if(q1=='d9&&q0=='d9)
            q1<=0;
        else if(ena[1]) 
            q1<=q1+1;
        else
            q1<=q1;
    end
     always@(posedge clk) begin
        if(reset)
            q2<=0;
         else if(q2=='d9&&q1=='d9&&q0=='d9)
            q2<=0;
         else if(ena[2]) 
            q2<=q2+1;
        else
            q2<=q2;
    end
     always@(posedge clk) begin
        if(reset)
            q3<=0;
         else if(q3=='d9&&q2=='d9&&q1=='d9&&q0=='d9)
            q3<=0;
         else if(ena[3]) 
            q3<=q3+1;
        else
            q3<=q3;
    end

       
endmodule

8.count_clock

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

wire ss_en,ss_60_en;       
reg [3:0] ss_one,ss_ten;   

wire mm_en,mm_60_en;
reg [3:0] mm_one,mm_ten; 

wire hh_en,pm_en;            
reg [3:0] hh_one,hh_ten; 

assign ss = {ss_ten,ss_one};
assign mm = {mm_ten,mm_one};
assign hh = {hh_ten,hh_one};
always @(posedge clk) begin
    if (reset) begin
        ss_one <= 4'b0;
    end
    else if(ena) begin
        if (ss_one == 4'd9) begin
            ss_one <= 4'b0;
        end
        else
            ss_one <= ss_one + 1'b1;
    end
end
assign ss_en = ((ss_one == 4'd9) && ena) ? 1'b1 : 1'b0;

always @(posedge clk) begin
    if (reset) begin
        ss_ten <= 4'b0;
    end
    else if(ss_en) begin
        if ((ss_one == 4'd9) && (ss_ten == 4'd5) && ena) begin
            ss_ten <= 4'b0;
        end
        else
            ss_ten <= ss_ten + 1'b1;
    end
end
assign ss_60_en = ((ss_one == 4'd9) && (ss_ten == 4'd5) && ena) ? 1'b1 : 1'b0;


always @(posedge clk) begin
    if (reset) begin
        mm_one <= 4'b0;
    end
    else if(ss_60_en) begin
        if (mm_one == 4'd9) begin
            mm_one <= 4'b0;
        end
        else
            mm_one <= mm_one + 1'b1;
    end
end
assign mm_en = ((mm_one == 4'd9) && (ss_one == 4'd9) && (ss_ten == 4'd5) && ena) ? 1'b1 : 1'b0;

always @(posedge clk) begin
    if (reset) begin
        mm_ten <= 4'b0;
    end
    else if(mm_en) begin
        if ((mm_one == 4'd9) && (mm_ten == 4'd5) && ena && (ss_one == 4'd9) && (ss_ten == 4'd5)) begin
            mm_ten <= 4'b0;
        end
        else
            mm_ten <= mm_ten + 1'b1;
    end
end
assign mm_60_en = ((mm_one == 4'd9) && (mm_ten == 4'd5) && ena && (ss_one == 4'd9) && (ss_ten == 4'd5)) ? 1'b1 : 1'b0;




always @(posedge clk) begin
    if (reset) begin
        hh_one <= 4'd2;
    end
    else if(mm_60_en) begin
        if ((hh_one == 4'd2) && (hh_ten == 4'd1) && (mm_one == 4'd9) && (mm_ten == 4'd5) && ena && (ss_one == 4'd9) && (ss_ten == 4'd5)) begin
            hh_one <= 4'd1;
        end
        else if ((hh_one == 4'd9) && (hh_ten == 4'd0) && (mm_one == 4'd9) && (mm_ten == 4'd5) && ena && (ss_one == 4'd9) && (ss_ten == 4'd5)) begin
            hh_one <= 4'd0;
        end
        else
            hh_one <= hh_one + 1'b1;
    end
end
assign hh_en = ((hh_one == 4'd9) && (hh_ten == 4'd0) && (mm_one == 4'd9) && (mm_ten == 4'd5) && ena && (ss_one == 4'd9) && (ss_ten == 4'd5)) ? 1'b1 : 1'b0;

always @(posedge clk) begin
    if (reset) begin
        hh_ten <= 4'b1;
    end
    else if ((hh_one == 4'd2) && (hh_ten == 4'd1) && (mm_one == 4'd9) && (mm_ten == 4'd5) && ena && (ss_one == 4'd9) && (ss_ten == 4'd5)) begin
        hh_ten <= 4'd0;
    end   
    else if(hh_en) begin
        hh_ten <= 4'd1;
    end
end

assign pm_en = ((hh_one == 4'd1) && (hh_ten == 4'd1) && (mm_one == 4'd9) && (mm_ten == 4'd5)&& (ss_one == 4'd9) && (ss_ten == 4'd5) && ena) ? 1'b1 : 1'b0;
always @(posedge clk) begin
    if (reset) begin
        pm <= 1'b0;
    end
    else    if (pm_en) begin
        pm <= ~pm;
    end
        
end
endmodule