网址:https://hdlbits.01xz.net/wiki/Countbcd
module bcdcount
( input clk,
input reset,
input ena,
output reg [3:0] q
);
always @(posedge clk)begin
if (reset == 1'b1)
q <= 4'b0;
else if (ena == 1'b1)
begin
if (q == 4'h9)
q <= 4'b0;
else
q <= q + 1'b1 ;
end
end
endmodule
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
reg [3:0] q1,q2,q3,q4;
bcdcount bcdcount1 (.clk(clk),
.reset(reset),
.ena(1'b1),
.q(q1));
bcdcount bcdcount2 (.clk(clk),
.reset(reset),
.ena(q1==4'h9),
.q(q2));
bcdcount bcdcount3 (.clk(clk),
.reset(reset),
.ena(q2==4'h9 && q1==4'h9) ,
.q(q3));
bcdcount bcdcount4 (.clk(clk),
.reset(reset),
.ena(q3==4'h9 &&q2==4'h9 && q1==4'h9) ,
.q(q4));
assign ena = {{q3==4'h9 && q2==4'h9 && q1==4'h9},{q2==4'h9 && q1==4'h9}, {q1==4'h9}};
assign q = {q4,q3,q2,q1};
endmodule