FPGA笔记1&&vivado工程建立步骤

 

时钟和频率

1KHZ     1ms      1毫秒

1MHZ     1us       1微秒

1GHZ      1ns       1纳秒

1s = 10（3）ms    =  10（6）us    = 10（9）ns

复位

同步复位：按下复位键后，等待时钟上升沿后复位才有效

异步复位：复位键有效后即复位，与时钟沿无关

 

//CHN: 异步上沿复位
always @ (posedge clk or posedge rst) begin
    if (rst) begin
        
//CHN: 异步下沿复位
always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        
//CHN: 同步上沿复位
always @ (posedge clk) begin
    if (rst) begin
        
//CHN: 同步下沿复位
always @ (posedge clk) begin
    if (~rst_n) begin

 

always @ (posedge clk) begin
    if (rst) begin
        r_data_valid    <= 1'b0;
    end else begin
        r_data_valid    <= i_data_valid;
    end
end

always @ (posedge clk) begin
    r_data_valid_4ff    <= {r_data_valid_4ff[2:0],r_data_valid};
end

always @ (posedge clk) begin
    if (rst) begin
        r_out_valid <= 1'b0;
    end else begin
        r_out_valid <= r_data_valid_4ff[3];
    end
end