Verilog代码
//按键按下为高电平
module xiaodou(clk_in,button_in,button);//消抖模块
//输入输出端口说明
input clk_in,button_in;//四个按键输入
output button;
reg[20:0] count_low;//按键未按下(低电平)的计数变量
reg[20:0] count_high;//按键按下(高电平)的计数变量
reg button_reg;
reg button_reg_d0;
always@(posedge clk_in)begin //100MHz的时钟
if(button_in==1'b0) //按键0未按下的计数变量加1
count_low<=count_low+21'b1;
else //否则当按键0按下,未按下的计数变量清0
count_low<=0;
end
always@(posedge clk_in)begin
if(button_in==1'b1) //按键0按下后的计数变量加1
count_high<=count_high+21'b1;
else //否则当按键0未按下,按下后的计数变量清0
count_high<=0;
end
always@(posedge clk_in)begin
if(count_high==1_999_999) //当按键0按下时间约20ms时,说明确实有按键被按下
button_reg<=1;
else if(count_low==1_999_999) //按键0未按下时间越20ms,说明没有按键按下
button_reg<=0;
end
always @(posedge clk_in)begin
button_reg_d0 <= button_reg;
end
assign button=button_reg & !button_reg_d0; //将按键0是否按下的结果及时输出
endmodule