Verilog 刷题 -Fsm ps2

 

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //
    reg [1:0]state;
    reg  [1:0]next_state;
    parameter w=0,r1=1,r2=2,r3=3;
    always@(*)begin
        case(state)
            w:next_state = in[3]?r1:w;
            r1:next_state = r2;
            r2:next_state = r3;
            r3:next_state = in[3]?r1:w;
        endcase
    end
    always@(posedge clk)begin
        if(reset)state <= w;
        else state <= next_state;
    end
    assign done = (state == r3);
        
    // State transition logic (combinational)

    // State flip-flops (sequential)
 
    // Output logic

endmodule